公开(公告)号：US08347259B1

公开(公告)日：2013-01-01

申请号：US13193721

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Critical circuit blocks are identified in a chip design layout, and are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each critical circuit block within each marked region. Each multiplicate layer includes a different type of variant for each identified critical circuit block. The different types of variants correspond to different types of optimization goals to address different issues in circuit performance. Circuit simulation is performed with each type of variants in combination with adjacent circuit blocks as provided in original design. In each marked region, the results of the circuit simulations are evaluated to determine an optimal type among the variants. The optimal type is retained in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant circuit blocks to provide local circuit optimization.

Abstract translation: 关键电路块以芯片设计布局标识，并标记标识区域的标记层。 为每个标记区域内的每个关键电路块生成多重层。 每个多重层包括用于每个识别的关键电路块的不同类型的变体。 不同类型的变体对应于不同类型的优化目标，以解决电路性能中的不同问题。 在原始设计中提供的每种类型的变体与相邻电路块的组合进行电路仿真。 在每个标记区域中，评估电路模拟的结果以确定变体中的最佳类型。 最佳类型保留在每个标记区域中，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体电路块以提供本地电路优化。

公开(公告)号：US08458625B2

公开(公告)日：2013-06-04

申请号：US13193716

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G03F7/70433 ,  G03F7/705

Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Abstract translation: 与光刻层相关的潜在平版印刷热点由识别标记区域的标记层标记。 为每个标记区域中的光刻级别中的每个设计形状生成多重层。 每个多重层包括在光刻层级中的每个设计形状的不同类型的变体。 不同类型的变体对应于不同的设计环境。 在长距离效应的约束下，每种类型的变体进行平版印刷模拟，例如由光刻层面中的相邻形状提供的图案密度。 在每个标记区域中，评估光刻模拟的结果以确定变体中的最佳类型。 为每个标记区域中的光刻级别保留最佳类型，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体形状以提供局部光刻优化。

公开(公告)号：US20130031519A1

公开(公告)日：2013-01-31

申请号：US13193716

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G03F7/70433 ,  G03F7/705

Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Abstract translation: 与光刻层相关的潜在平版印刷热点由识别标记区域的标记层标记。 为每个标记区域中的光刻级别中的每个设计形状生成多重层。 每个多重层包括在光刻层级中的每个设计形状的不同类型的变体。 不同类型的变体对应于不同的设计环境。 在长距离效应的约束下，每种类型的变体进行平版印刷模拟，例如由光刻层面中的相邻形状提供的图案密度。 在每个标记区域中，评估光刻模拟的结果以确定变体中的最佳类型。 为每个标记区域中的光刻级别保留最佳类型，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体形状以提供局部光刻优化。

公开(公告)号：US08473885B2

公开(公告)日：2013-06-25

申请号：US13413759

申请日：2012-03-07

Applicant: John M. Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woeltgens

Inventor： John M. Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woeltgens

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5072

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

公开(公告)号：US20120227019A1

公开(公告)日：2012-09-06

申请号：US13471789

申请日：2012-05-15

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract translation: 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US08214770B2

公开(公告)日：2012-07-03

申请号：US12357648

申请日：2009-01-22

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

Abstract translation: 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。

公开(公告)号：US20120144356A1

公开(公告)日：2012-06-07

申请号：US13371537

申请日：2012-02-13

Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC: G06F9/455

CPC classification number: G06F17/5009 ,  G06F2217/10

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US07935638B2

公开(公告)日：2011-05-03

申请号：US12566043

申请日：2009-09-24

Applicant: James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/32139 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3185

Abstract: Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions.

Abstract translation: 用于增强不同基底区域中异质特征之间的周长与表面积之比的均匀性的方法和结构。 衬底上的至少一种形状包括有效减少第一衬底区域中的特征与第二衬底区域中的特征之间的周边表面积比的差异的附加边缘。 周边至表面积比的改善的均匀性降低了跨越第一和第二基底区域中的特征沉积的共形层的厚度变化。

公开(公告)号：US07890906B2

公开(公告)日：2011-02-15

申请号：US12117761

申请日：2008-05-09

Applicant: Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.

Abstract translation: 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

公开(公告)号：US07849433B2

公开(公告)日：2010-12-07

申请号：US12117771

申请日：2008-05-09

Applicant: Laura S. Chadwick ,  James A. Culp ,  David J Hathaway ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  David J Hathaway ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5072

Abstract: Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.

Abstract translation: 公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。 该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。 然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。 这种重新配置以基本维持期望的去耦电容的方式执行。 由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。 本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。