Excess-Fours Processing in Direct Digital Synthesizer Implementations
    1.
    发明申请
    Excess-Fours Processing in Direct Digital Synthesizer Implementations 有权
    直接数字合成器实现中的四分之一处理

    公开(公告)号:US20160161975A1

    公开(公告)日:2016-06-09

    申请号:US15006088

    申请日:2016-01-25

    Abstract: Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided. Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to he responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.

    Abstract translation: 提供了具有多个子相位累加器的分相相位累加器的系统和方法。 每个子相位累加器接收频率控制字的一部分。 第一子相位累加器包括第一寄存器,其余子相位累加器包括寄存器和溢出寄存器。 在每个离散时间点,第一子相位累加器被配置为响应于该离散时间点处的频率控制字的第一部分以及在紧接的先前离散时间点处的第一子相位累加器值,以及 剩余子相累加器中的每一个被配置为响应于在该离散时间点的频率控制字的对应部分的值以及在紧接的先前离散时间点处的相同的第二子相位累加器值。

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