公开(公告)号：US5689471A

公开(公告)日：1997-11-18

申请号：US579079

申请日：1995-12-22

申请人： Peter H. Voss ,  Jeffrey L. Linden

发明人： Peter H. Voss ,  Jeffrey L. Linden

IPC分类号： G11C7/14 ,  G11C11/412 ,  G11C11/34

CPC分类号： G11C11/412 ,  G11C7/14

摘要： A dummy cell in a memory array. The memory array includes a storage element for storing one of a first and a second state. The storage element is coupled to circuitry for reading the first or second state from the storage element. The storage element draws a first current when the first state is read by the circuitry. The storage element and circuitry are further coupled to the dummy cell which provides a reference voltage when the circuitry reads the first or second state from the storage element. The dummy cell draws a second current when the circuitry reads the first or second state from the storage element. The second current is not equivalent to the first the first current. In one embodiment, the dummy cell draws approximately half the current that the storage element draws when the circuitry reads the first state from the storage element. In another embodiment, the dummy cell includes a pass transistor which has a width which is approximately half the width of a pass transistor included in the storage element. In still another embodiment, the dummy cell includes a pass transistor which has a length which is approximately twice the length of a pass transistor included in the storage element.

摘要翻译： 存储器阵列中的虚拟单元。 存储器阵列包括用于存储第一状态和第二状态之一的存储元件。 存储元件耦合到用于从存储元件读取第一或第二状态的电路。 当电路读取第一状态时，存储元件绘制第一电流。 当电路从存储元件读取第一或第二状态时，存储元件和电路进一步耦合到虚拟单元，该虚拟单元提供参考电压。 当电路从存储元件读取第一或第二状态时，虚拟单元抽取第二电流。 第二个电流不等于第一个电流。 在一个实施例中，当电路从存储元件读取第一状态时，虚拟单元消耗存储元件吸引的电流的大约一半。 在另一个实施例中，虚设单元包括通过晶体管，其宽度大约是包含在存储元件中的传输晶体管的宽度的一半。 在另一个实施例中，虚设单元包括通过晶体管，其长度大约是包含在存储元件中的通过晶体管的长度的两倍。

公开(公告)号：US5453950A

公开(公告)日：1995-09-26

申请号：US377952

申请日：1995-01-24

申请人： Peter H. Voss ,  Jeffrey L. Linden

发明人： Peter H. Voss ,  Jeffrey L. Linden

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/40

CPC分类号： G11C11/412

摘要： Static random access memory cells (SRAMS) containing five MOS transistors are configured in a memory array such that only three bitlines are required for two cells. A first bitline is coupled to a first side of a first memory cell, and a second bitline is coupled to a first side of the second memory cell. The first and second memory cells share either a common power bitline or a common ground bitline. A control circuit executes a special write operation to write a low logic level on the second side of the memory cells. The control circuit is coupled to the first, second, and third bitlines to generate a first differential voltage across the memory cells that is lower than the operating voltage on the third bitline and to generate a second voltage lower than the operating voltage on the second bitline when storing a low logic level on the second side of the first storage cell. To perform a special write operation on the second storage cell, the control circuit generates the first differential voltage on the third bitline and the second voltage on the first bitline.

摘要翻译： 包含五个MOS晶体管的静态随机存取存储单元（SRAMS）配置在存储器阵列中，使得两个单元仅需要三个位线。 第一位线耦合到第一存储器单元的第一侧，并且第二位线耦合到第二存储器单元的第一侧。 第一和第二存储器单元共享公共功率位线或公共地线。 控制电路执行特殊写入操作以在存储器单元的第二侧上写入低逻辑电平。 控制电路耦合到第一，第二和第三位线以在存储器单元两端产生低于第三位线上的工作电压的第一差分电压，并产生低于第二位线上的工作电压的第二电压 当在第一存储单元的第二侧存储低逻辑电平时。 为了在第二存储单元上执行特殊的写入操作，控制电路在第三位线上产生第一差分电压，并在第一位线上产生第二电压。