公开(公告)号：US06690432B2

公开(公告)日：2004-02-10

申请号：US09833895

申请日：2001-04-12

申请人： Peter J. M. Janssen ,  Jeffrey A. Shimizu ,  John E. Dean ,  Douglas A. Stanton

发明人： Peter J. M. Janssen ,  Jeffrey A. Shimizu ,  John E. Dean ,  Douglas A. Stanton

IPC分类号： H04N931

CPC分类号： H04N9/312 ,  H04N9/3117

摘要： A prism is mounted onto a motor without regard to its rotation angle relative to the motor index. Its position is electronically set later after construction of the optical path. A motor controller is used to control the rotation of the prism. This motor controller keeps the prism spinning at a constant velocity and positions the prism phase (rotation angle versus time). A variable offset is used to position the absolute prism rotation as a function of time. The phase may be advanced or delayed by an operator during set up. Each prism has its own phase. The phase of each prism in the system is set so that the illumination pattern correctly matches the video addressing of the panel. This is a one time set up during construction. The correct positions are set, and stored in non-volatile memory for life.

摘要翻译： 棱镜安装在马达上，而不考虑其相对于马达索引的旋转角度。 它的位置在光路构建后稍后进行电子设置。 电机控制器用于控制棱镜的旋转。 该电机控制器保持棱镜以恒定的速度旋转并定位棱镜相位（旋转角度对时间）。 使用可变偏移量将绝对棱镜旋转定位为时间的函数。 在设置期间，操作者可以提前或延迟该阶段。 每个棱镜都有自己的相位。 系统中的每个棱镜的相位被设置为使得照明图案正确地匹配面板的视频寻址。 这是施工期间的一次设置。 设置正确的位置，并将其存储在非易失性存储器中。

公开(公告)号：US06891545B2

公开(公告)日：2005-05-10

申请号：US10215067

申请日：2002-08-08

申请人： John E. Dean

发明人： John E. Dean

IPC分类号： G06F12/00 ,  G09G3/20 ,  G09G5/00 ,  G09G5/393 ,  H04N1/46 ,  G09G5/36

CPC分类号： G09G5/005 ,  G09G5/006 ,  G09G5/393 ,  G09G2310/0235 ,  G09G2360/128

摘要： A system and method for managing memory in display processing circuit for use with a color sequential display. The system comprises: a shared memory; and a storage queue coupled to the shared memory, wherein the storage queue includes: a system for receiving and storing alternating packets of color-specific video data in the storage queue; and a system for separately reading contiguous sets color-specific packets from the storage queue to the shared memory.

摘要翻译： 一种用于管理用于彩色顺序显示的显示处理电路中的存储器的系统和方法。 该系统包括：共享存储器; 以及耦合到所述共享存储器的存储队列，其中所述存储队列包括：用于在所述存储队列中接收和存储颜色特定视频数据的交替分组的系统; 以及用于分开读取将存储队列中的颜色特定分组连续设置到共享存储器的系统。

公开(公告)号：US06384817B1

公开(公告)日：2002-05-07

申请号：US09469455

申请日：1999-12-21

申请人： Peter J. Janssen ,  Lucian Remus Albu ,  John E. Dean

发明人： Peter J. Janssen ,  Lucian Remus Albu ,  John E. Dean

IPC分类号： G09G500

CPC分类号： G09G3/2011 ,  G02F1/13306 ,  G09G3/3685 ,  G09G2310/0259 ,  G09G2320/02

摘要： In an electro-optic display device, such as a liquid crystal display device which serves as a modulator for projected light, a global ramp generator is used in conjunction with track and hold circuits to convert incoming digital display signals to analog signals, and to address the individual pixels of the display device with such analog signals. A plurality of column drivers, each coupled to the ramp generator and to the pixels in a column of the display device, track and hold the ramp voltage signal when it reaches a value corresponding to the desired brightness level of a particular pixel in the respective column. At least one current source is provided, coupled to the signal source output, for supplying current to the signal source output, as needed, to compensate for switching the capacitive load of the column drivers on and off. As a result, transient voltages in the ramp signal are avoided.

摘要翻译： 在诸如用作投影光的调制器的液晶显示装置的电光显示装置中，全局斜坡发生器与轨道和保持电路结合使用以将输入的数字显示信号转换为模拟信号，并且寻址 具有这种模拟信号的显示装置的各个像素。 每个耦合到斜坡发生器和显示装置的列中的像素的列驱动器当其达到对应于相应列中的特定像素的期望亮度水平的值时跟踪并保持斜坡电压信号 。 提供耦合到信号源输出的至少一个电流源，用于根据需要向信号源输出提供电流，以补偿对列驱动器的容性负载的开关。 结果，避免了斜坡信号中的瞬态电压。

公开(公告)号：US5963261A

公开(公告)日：1999-10-05

申请号：US641057

申请日：1996-04-29

申请人： John E. Dean

发明人： John E. Dean

IPC分类号： H04N5/46 ,  H04N5/44 ,  H04N7/01

CPC分类号： H04N7/0122

摘要： A circuit that is easily configured to convert from a progressive scan image, e.g., at a resolution of 1280.times.720, to an interlaced image scan, e.g., at an interlaced resolution of 1920.times.1080 (1920.times.540 per field), or visa-versa. One arrangement of the circuit employs multiplexers so that the two conversion modes share the available hardware. The circuit is only marginally more complex than a circuit that can only do the conversion in one direction. The quality of the progressive-to-interlace conversion is acceptable for high-end interlaced display systems and the quality of the interlace-to-progressive conversion is at least high enough for "mid-range" progressive display systems.

摘要翻译： 容易配置为例如以1280×720的分辨率从逐行扫描图像转换为隔行图像扫描的电路，例如以1920×1080（每场1920x540）的交错分辨率，或反之亦然。 该电路的一种布置采用多路复用器，使得两种转换模式共享可用的硬件。 该电路仅比只能在一个方向进行转换的电路复杂得多。 逐行扫描转换的质量对于高端隔行显示系统是可以接受的，并且交错到逐行转换的质量至少足够高于“中档”逐行显示系统。

公开(公告)号：US06462728B1

公开(公告)日：2002-10-08

申请号：US09469449

申请日：1999-12-21

申请人： Peter J. Janssen ,  John E. Dean ,  Lucian Remus Albu

发明人： Peter J. Janssen ,  John E. Dean ,  Lucian Remus Albu

IPC分类号： G09G336

CPC分类号： G09G3/2011 ,  G09G3/20 ,  G09G3/2025 ,  G09G3/2051 ,  G09G3/3688 ,  G09G2310/0259 ,  G09G2310/027

摘要： In an electro-optic display device, such as a liquid crystal display device which serves as a modulator for projected light, a global DAC controlled ramp generator is used in conjunction with track and hold circuit for each column of the display to convert incoming digital display signals to analog signals for all columns. Row address circuitry addresses each row of the display, thereby to address the individual pixels of the display device with such analog signals. The limitation on an increase in frame rate, resulting from the finite conversion time (cycle time) of the DAC, is overcome by reducing the grey scale resolution, thus reducing the number of times that the DAC must convert a digital number to an analog voltage during each ramp cycle, and restoring the original resolution using temporal “dithering”—i.e., interpolation between the brightness levels of pixels in successive frames.

摘要翻译： 在诸如用作投影光的调制器的液晶显示装置的电光显示装置中，全局DAC控制斜坡发生器与显示器的每列的跟踪和保持电路一起使用以转换输入的数字显示 信号到所有列的模拟信号。 行地址电路寻址显示器的每行，由此用这种模拟信号寻址显示设备的各个像素。 由于DAC的有限转换时间（周期时间）导致的帧速率增加的限制通过降低灰度分辨率来克服，从而减少DAC必须将数字数字转换为模拟电压的次数 在每个斜坡周期期间，并且使用时间“抖动”恢复原始分辨率，即在连续帧中的像素的亮度级之间的内插。

公开(公告)号：US06803902B2

公开(公告)日：2004-10-12

申请号：US10114495

申请日：2002-04-02

申请人： Peter J. Janssen ,  John E. Dean

发明人： Peter J. Janssen ,  John E. Dean

IPC分类号： G09G336

CPC分类号： H04N9/3117

摘要： A uniform phase relation restoration method for a. scrolling color projection system wherein the addressing sequence of an LCD panel is altered to change the sweep rate of any one primary color relative to the other two primary colors to momentarily increase the sweep speed of the one color channel while correspondingly decreasing the sweep speed of the other two color channels.

摘要翻译： 一种均匀相位恢复方法。 滚动彩色投影系统，其中改变LCD面板的寻址顺序以改变相对于其它两个基色的任何一个原色的扫描速率，以瞬间增加一个颜色通道的扫描速度，同时相应地降低 其他两个颜色通道。

公开(公告)号：US06734868B2

公开(公告)日：2004-05-11

申请号：US10028380

申请日：2001-12-21

申请人： Viktor L. Gornstein ,  John E. Dean

发明人： Viktor L. Gornstein ,  John E. Dean

IPC分类号： G06F1206

CPC分类号： G09G3/20 ,  G09G2310/0221 ,  G09G2310/0297 ,  G09G2352/00

摘要： An address generator for a pixel shuffler used in a relective liquid crystal display (RLCD) digital video system, and a pixel shuffler incorporating such an address generator. The address generator includes a small, dual port SRAM 160×8, a combinatorial converter having a pair of inputs and an output representing a predetermined relationship of the inputs, a pixel counter with a pair of decoders, a line counter, a computing block for selectively implementing a mirror reflection of the pixel addresses, as well as a plurality of D flip flops and logic elements. The pixel shuffler operates in read-modify-write mode, whereby any address location of memory is read and immediately overwritten with the new data. This permits operation with only one bank of SRAM 320×96 rather than the customary two banks for prior art pixel shufflers using the so-called Ping Pong method.

摘要翻译： 用于反射型液晶显示器（RLCD）数字视频系统中的像素洗牌器的地址发生器，以及包含这样的地址发生器的像素洗牌器。 地址发生器包括一个小的双端口SRAM 160x8，组合转换器，具有一对输入和表示输入的预定关系的输出，具有一对解码器的像素计数器，行计数器，用于选择性地执行的计算块 像素地址的镜像反射，以及多个D触发器和逻辑元件。 像素洗牌器以读 - 修改 - 写入模式运行，从而读取存储器的任何地址位置并立即用新数据覆盖。 这允许使用所谓的乒乓方法仅使用一行SRAM 320x96而不是现有技术的像素洗牌器的常规两个组。