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1.发明申请公开(公告)号：US20090183130A1
公开(公告)日：2009-07-16
申请号：US11972923
申请日：2008-01-11
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.
摘要翻译： 一种用于电子电路的层次分析的方法包括选择通用设计模型（GDM）的多个抽象层中的第一个抽象层。 GDM包括在多个抽象级别的电子电路的第一设计描述和被组织成子块的多个焦点。 该方法选择多个焦点的第一焦点以选择第一子块。 该方法识别所选择的第一子块中不完整的电子电路。 该方法产生第一子块的第二设计描述以排除所识别的不完整电子电路，其中第二设计描述适用于电子设计分析（EDA）。 该方法存储生成的第二设计描述供后续使用。 随后的迭代因此包括在先前迭代中不完整的电路的所有组件。
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2.发明授权公开(公告)号：US07870515B2
公开(公告)日：2011-01-11
申请号：US11972923
申请日：2008-01-11
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.
摘要翻译： 一种用于电子电路的层次分析的方法包括选择通用设计模型（GDM）的多个抽象层中的第一个抽象层。 GDM包括在多个抽象级别的电子电路的第一设计描述和被组织成子块的多个焦点。 该方法选择多个焦点的第一焦点以选择第一子块。 该方法识别所选择的第一子块中不完整的电子电路。 该方法产生第一子块的第二设计描述以排除所识别的不完整电子电路，其中第二设计描述适用于电子设计分析（EDA）。 该方法存储生成的第二设计描述供后续使用。 随后的迭代因此包括在先前迭代中不完整的电路的所有组件。
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3.发明授权Timing point selection for a static timing analysis in the presence of interconnect electrical elements 有权在存在互连电气元件的情况下进行静态时序分析的时序点选择公开(公告)号：US08201120B2
公开(公告)日：2012-06-12
申请号：US12652338
申请日：2010-01-05
申请人： Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
发明人： Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
CPC分类号： G06F17/5031
摘要： A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.
摘要翻译： 一种用于选择电气互连网络中用于静态时序分析的电气仿真中的定时点的方法和系统，以提高精度。 本发明的方法包括发现在互连的电气模型中的阻塞点，所述互连的所有路径对于所述路由器必须在某些类型的网络上通过。 然后，该方法使用其存在的阻塞点电子节点作为驱动网络的逻辑门的输出定时点。 该方法解决了由于同一互连网上的不同驱动器引脚之间的电阻引起的不准确性的问题，尽管它也可以应用于解决由于与相同接收器定时点相关联的不同接收器引脚之间的电阻引起的类似不准确性。 它还适用于与其他双端口寄生元件的互连，仅在网络上的接收器引脚的子集需要精确的定时的情况下，以及一组电气节点而不是单个节点将所有路径从 驱动程序到网络上的接收器。
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4.发明申请Timing Point Selection For A Static Timing Analysis In The Presence Of Interconnect Electrical Elements 有权在互连电气元件存在下的静态时序分析的时序点选择公开(公告)号：US20110167395A1
公开(公告)日：2011-07-07
申请号：US12652338
申请日：2010-01-05
申请人： Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
发明人： Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.
摘要翻译： 一种用于选择电气互连网络中用于静态时序分析的电气仿真中的定时点的方法和系统，以提高精度。 本发明的方法包括发现在互连的电气模型中的阻塞点，所述互连的所有路径对于所述路由器必须在某些类型的网络上通过。 然后，该方法使用其存在的阻塞点电子节点作为驱动网络的逻辑门的输出定时点。 该方法解决了由于同一互连网上的不同驱动器引脚之间的电阻引起的不准确性的问题，尽管它也可以用于解决由于与相同接收器定时点相关联的不同接收器引脚之间的电阻引起的类似不准确性。 它还适用于与其他双端口寄生元件的互连，仅在网络上的接收器引脚的子集需要精确的定时的情况下，以及一组电气节点而不是单个节点将所有路径从 驱动程序到网络上的接收器。
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5.发明授权Method for reducing RC parasitics in interconnect networks of an integrated circuit 失效降低集成电路互连网络中RC寄生效应的方法公开(公告)号：US06763504B2
公开(公告)日：2004-07-13
申请号：US10237328
申请日：2002-09-06
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor. It also preserves the delays at all nodes in the interconnect network apart from the two ends of the resistor selected for shorting.
摘要翻译： 描述了在内部节点消除之后进一步减少互连网络中的RC寄生效应的方法。 最初选择一个电阻作为短路的候选，并且确定电阻器两端的累积延迟误差是否小于预定阈值。 该阈值必须是通过内部节点消除技术选择的时间常数阈值的一小部分，以便限制累积延迟误差的增长。 本发明的一个重要方面是用于改变下游电阻值的公式的简单性，即，电阻器的值的乘积与电阻器的两端的累积下游电容的比值，其值为 改变了 更新下游电阻值的这一特定选择可以使由于所选择的电阻器的短路导致的每个节点的延迟误差的绝对值最小化。 它还保留互连网络中所有节点之间的延迟，除了选择短路的电阻器的两端之外。
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公开(公告)号：US08655634B2
公开(公告)日：2014-02-18
申请号：US12721227
申请日：2010-03-10
申请人： David J. Hathaway , Vasant Rao , Ronald D. Rose , Ali Sadigh , Jeffrey P. Soreff , David W. Winston
发明人： David J. Hathaway , Vasant Rao , Ronald D. Rose , Ali Sadigh , Jeffrey P. Soreff , David W. Winston
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/509 , G06F2217/84
摘要： A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.
摘要翻译： 一种用于建模晶体管网络中负载CCC（通道连接部件）的负载影响的系统，方法和程序产品。 公开了一种系统，其包括分析系统，该分析系统确定负载CCC中针对正在确定负载条件的驱动CCC的转变或状态的网络的允许逻辑状态和转换功能; 跟踪系统，从一组输入端子遍历负载CCC中的路径; 以及元件替换系统，其替换负载CCC中的电路元件以创建建模的CCC，其中电路元件替换基于沿着跟踪遇到的电路元件的类型，以及连接到遇到的电路元件的网络的状态和转换功能 。
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公开(公告)号：US20110224965A1
公开(公告)日：2011-09-15
申请号：US12721227
申请日：2010-03-10
申请人： David J. Hathaway , Vasant Rao , Ronald D. Rose , Ali Sadigh , Jeffrey P. Soreff , David W. Winston
发明人： David J. Hathaway , Vasant Rao , Ronald D. Rose , Ali Sadigh , Jeffrey P. Soreff , David W. Winston
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/509 , G06F2217/84
摘要： A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.
摘要翻译： 一种用于建模晶体管网络中负载CCC（通道连接部件）的负载影响的系统，方法和程序产品。 公开了一种系统，其包括分析系统，该分析系统确定负载CCC中针对正在确定负载条件的驱动CCC的转变或状态的网络的允许逻辑状态和转换功能; 跟踪系统，从一组输入端子遍历负载CCC中的路径; 以及元件替换系统，其替换负载CCC中的电路元件以创建建模的CCC，其中电路元件替换基于沿着跟踪遇到的电路元件的类型，以及连接到遇到的电路元件的网络的状态和转换功能 。
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8.发明授权Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect 有权混合线性线模型方法来调整具有RC互连的电路的晶体管宽度公开(公告)号：US07325210B2
公开(公告)日：2008-01-29
申请号：US11077043
申请日：2005-03-10
申请人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey P. Soreff , Patrick M. Williams , David J. Hathaway
发明人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey P. Soreff , Patrick M. Williams , David J. Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068
摘要： A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs. To prevent “de-tuning” that typically occurs when all Rs are shorted, ‘wire-adjusts’ are provided that make the initial timing results using the Gradient oriented simulator on the shorted netlist match the timing results using Timing oriented simulator on the original netlist. This permits the optimizer sense initially the correct set of critical timing paths, and more significantly, it permits the wire-adjusts keep track of the changing transistor widths to guide the optimizer during the iterations until convergence is achieved.
摘要翻译： 描述了用于调谐由RC互连链接的电路的晶体管宽度的混合线性线模型。 在调谐过程中，该方法使用两个嵌入式模拟器，其中包含电阻（Rs）。 面向计时的模拟器仅用于包含所有Rs的原始网表的时序目的。 然后，一个面向梯度的模拟器仅在修改后的网表上运行，所有的Rs都已经短路，并在调谐器的迭代循环内计算梯度。 目前的混合方法实现了计算速度的显着提高。 面向时序的模拟器只需要具有Rs的时间网络列表即可快速准确，但无法有效地计算渐变。 梯度导向模拟器有效地计算梯度，但在Rs的存在下不能这样做。 为了防止所有Rs短路时通常发生的“去调谐”，提供“线调整”，使得在短路网表上使用面向梯度的模拟器的初始定时结果与使用定时模型的原始网表上的定时结果相匹配 。 这允许优化器最初感测正确的关键定时路径集合，并且更重要的是，它允许线路调整跟踪改变的晶体管宽度，以在迭代期间引导优化器直到实现收敛。
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9.发明授权公开(公告)号：US08607176B2
公开(公告)日：2013-12-10
申请号：US13088688
申请日：2011-04-18
CPC分类号： G06F17/5031
摘要： A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs.
摘要翻译： 一种用于构建延迟规则的方法，其中包括MIS模拟对静态时序分析的影响，降低成本。 本方法包括构建歪斜窗口，用于纯粹来自SIS数据的MIS惩罚，并根据使用案例中的倾斜度接近偏斜窗口的边缘来缩小规则使用期间的MIS惩罚。 该方法既适用于电路库的定时规则构造，也适用于宏的定时规则构造，其中宏中仅部分电路可能对宏输入之间的偏移敏感。
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10.发明申请SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS 有权系统和方法在静态时序分析期间的共同历史缓解公开(公告)号：US20110035714A1
公开(公告)日：2011-02-10
申请号：US12538229
申请日：2009-08-10
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.
摘要翻译： 一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。 一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入 对当前段的信号具有有界历史，至少一个传播和断言。 该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。
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