公开(公告)号：US20100017735A1

公开(公告)日：2010-01-21

申请号：US12218382

申请日：2008-07-15

申请人： Philip J. Erickson ,  Terrence Vincent Powderly ,  Andrew F. Sanderson ,  Gary L. Schwartz ,  Sebastian Serrano ,  James A. Sievert

发明人： Philip J. Erickson ,  Terrence Vincent Powderly ,  Andrew F. Sanderson ,  Gary L. Schwartz ,  Sebastian Serrano ,  James A. Sievert

IPC分类号： G06F15/76 ,  G06F3/048 ,  G06F9/02

CPC分类号： G06F9/5077

摘要： In general, techniques for performing decentralized hardware partitioning within a multiprocessing computing system are described herein. More specifically, the multiprocessing computing system comprises first and second independent computing cells, where the first cell comprises a first processor that calculates a partition identifier. The partition identifier uniquely identifies a partition to which the first cell belongs. The first cell also comprises a second processor that establishes the partition within the multiprocessing computing system based on the partition identifier, and executes a single operating system across the partition. In the event the established partition successfully includes the first and second cells, the first and second cells execute the single operating system across the partition. Because the cells themselves perform the partitioning process, scalability may be achieved more easily. Moreover, the overall cost of the system may be reduced because a dedicated processor may no longer be required to perform partitioning.

摘要翻译： 通常，这里描述了用于在多处理计算系统内执行分散硬件分区的技术。 更具体地，多处理计算系统包括第一和第二独立计算单元，其中第一单元包括计算分区标识符的第一处理器。 分区标识符唯一地标识第一小区所属的分区。 第一单元还包括基于分区标识符在多处理计算系统内建立分区的第二处理器，并跨越分区执行单个操作系统。 在建立的分区成功地包括第一和第二小区的情况下，第一和第二小区跨越分区执行单个操作系统。 因为单元本身执行分区过程，所以可以更容易地实现可扩展性。 此外，由于专用处理器可能不再需要执行分区，所以系统的整体成本可能会降低。

公开(公告)号：US20210014197A1

公开(公告)日：2021-01-14

申请号：US16509618

申请日：2019-07-12

申请人： Andrew F. Sanderson ,  Albert L. French ,  Sarah K. Inforzato ,  Lemoine D. Keiper, III

发明人： Andrew F. Sanderson ,  Albert L. French ,  Sarah K. Inforzato ,  Lemoine D. Keiper, III

IPC分类号： H04L29/06

摘要： In a cryptographically-segmented network, a server establishes a cryptographically-segmented communication channel for use by authorized endpoints in an operationally-deployed configuration. In response to a received endpoint-isolation command to isolate a first endpoint, the server de-authorizes the first endpoint from the channel of the operationally-deployed configuration. In response to the de-authorization, the server issues a configuration instruction to the first endpoint to join a first cryptographically-segmented isolation communication channel that is communicatively coupled with at least one monitoring endpoint configured to monitor operation of the first endpoint via the first cryptographically-segmented isolation communication channel.

公开(公告)号：US06792497B1

公开(公告)日：2004-09-14

申请号：US09851795

申请日：2001-05-09

申请人： Anthony P. Gold ,  Duane J. McCrory ,  Andrew F. Sanderson

发明人： Anthony P. Gold ,  Duane J. McCrory ,  Andrew F. Sanderson

IPC分类号： G06F1300

CPC分类号： G06F9/52

摘要： A crossbar structure for use in a multi-processor computer system to connect a plurality of processors to at least one shared resource. The crossbar structure comprises for each processor, a storage location for receiving from a respective processor a memory address of a lock control structure associated with the shared resource. When the processor needs to acquire a lock thereto, the crossbar structure, on behalf of the processor, performs memory operations on the lock control structure at the address specified in the storage location in order to acquire the lock on behalf of the processor.

摘要翻译： 一种用于在多处理器计算机系统中用于将多个处理器连接到至少一个共享资源的交叉开关结构。 交叉开关结构包括用于每个处理器的存储位置，用于从相应的处理器接收与共享资源相关联的锁定控制结构的存储器地址。 当处理器需要获得锁定时，代表处理器的交叉开关结构对存储位置中指定的地址的锁定控制结构执行存储器操作，以便代表处理器获取锁定。

公开(公告)号：US20160077937A1

公开(公告)日：2016-03-17

申请号：US14487669

申请日：2014-09-16

申请人： Robert F. Inforzato ,  Richard E. Blyler ,  Andrew F. Sanderson ,  Steven E. Clarke ,  Dwayne E. Ebersole ,  Steven L. Forbes ,  Andrew Ward Beale ,  Craig F. Russ ,  Craig R. Church ,  Derek W. Paul

发明人： Robert F. Inforzato ,  Richard E. Blyler ,  Andrew F. Sanderson ,  Steven E. Clarke ,  Dwayne E. Ebersole ,  Steven L. Forbes ,  Andrew Ward Beale ,  Craig F. Russ ,  Craig R. Church ,  Derek W. Paul

IPC分类号： G06F11/20

CPC分类号： G06F11/2028 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2046

摘要： A fabric computer method and system for recovering fabric computer node function. The fabric computer method includes monitoring a processing environment operating on a first Processor and Memory node within the fabric computer complex, detecting a failure of the first Processor and Memory node, and transferring the processing environment from the first Processor and Memory node to a second Processor and Memory node within the fabric computer complex in response to the detection of a failure of the first Processor and Memory node. The fabric computer system includes a first Processor and Memory node, a second Processor and Memory node coupled to the first Processor and Memory node, at least one input/output (I/O) and Networking node coupled to the first and second Processor and Memory nodes, and a fabric manager coupled to the first and second Processor and Memory nodes and the at least one I/O and Networking node. The fabric manager is configured to monitor a processing environment operating on the first Processor and Memory node, to receive notification of a failure of the first Processor and Memory node, and to transfer the processing environment from the first Processor and Memory node to the second Processor and Memory node in response to the detection of a failure of the first Processor and Memory node.

摘要翻译： 一种用于恢复织物计算机节点功能的织物计算机方法和系统。 结构计算机方法包括监视在结构计算机复合体内的第一处理器和存储器节点上操作的处理环境，检测第一处理器和存储器节点的故障，以及将处理环境从第一处理器和存储器节点传送到第二处理器 并且结构计算机内的内存节点复杂以响应检测到第一个处理器和存储器节点的故障。 结构计算机系统包括耦合到第一处理器和存储器节点的第一处理器和存储器节点，第二处理器和存储器节点，耦合到第一和第二处理器和存储器的至少一个输入/输出（I / O）和网络节点 节点和耦合到第一和第二处理器和存储器节点以及至少一个I / O和网络节点的结构管理器。 结构管理器被配置为监视在第一处理器和存储器节点上操作的处理环境，以接收第一处理器和存储器节点的故障的通知，并且将处理环境从第一处理器和存储器节点传送到第二处理器 和Memory节点，以响应检测到第一处理器和存储器节点的故障。

公开(公告)号：US20180351792A1

公开(公告)日：2018-12-06

申请号：US15613612

申请日：2017-06-05

申请人： James R. Hunter ,  Lilia A. Weber ,  Craig R. Church ,  Andrew F. Sanderson

发明人： James R. Hunter ,  Lilia A. Weber ,  Craig R. Church ,  Andrew F. Sanderson

IPC分类号： H04L12/24

摘要： This application relates in general to a method, apparatus, and article of manufacture for providing secure and redundant communications and processing for a collection of Internet of Things. An extreme way of providing high availability network functionality would be to duplicate every component of the network in a High Availability (HA) style cold standby mode. As long as there is some component, even one that is already in use performing other functions in the IoT network that can pinch hit for the failing component, then uptime can still be achieved and in a more cost effective way than completely duplicate HA fashion.

公开(公告)号：US5574730A

公开(公告)日：1996-11-12

申请号：US381046

申请日：1995-01-31

申请人： Joseph H. End, III ,  Todd M. Rimmer ,  Andrew F. Sanderson

发明人： Joseph H. End, III ,  Todd M. Rimmer ,  Andrew F. Sanderson

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536

摘要： Apparatus and method that incorporate bussed test access port interface into a system control interface for testing and controlling system logic boards in a manner that is fully compliant with the IEEE 1149.1 standard, while conserving system controller card signals. The apparatus incorporates six signals per interface, which includes the five standard signals as defined by IEEE 1149.1 standard plus a maintenance enable (ME) signal. Four of the standard signals, TCK, TMS, TDI and TRST* are bussed among multiple system logic boards, while the ME signals and the TDO signals are connected in a point-to-point manner between the system controller card and system logic boards. Instruction and data on the TCK, TMS, TDI, and TRST* signals are simultaneously bussed to all system logic boards. These four signals are received by each system logic board through an interface enable circuit, controlled by the ME signal line. If the instructions or data are intended for a specific system logic board, its corresponding ME signal line will be enabled to permit the passage of these signals and the resulting TDO signal through the interface enable circuit. This arrangement permits the incorporation of a bussed TAP interface into a system control interface for testing and controlling system logic boards that comply fully with the IEEE 1149.1 standard, while conserving the system controller card backplane pins dedicated to TAP signals, to two pins per system logic board plus four pins for the bussed TAP interface.

摘要翻译： 将总线测试访问端口接口结合到系统控制接口中的装置和方法，用于以完全符合IEEE 1149.1标准的方式测试和控制系统逻辑板，同时节省系统控制器卡信号。 该设备每个接口包含六个信号，其中包括由IEEE 1149.1标准定义的五个标准信号以及维护使能（ME）信号。 四个标准信号TCK，TMS，TDI和TRST *在多个系统逻辑板之间进行通信，而ME信号和TDO信号在系统控制器卡和系统逻辑板之间以点对点的方式连接。 TCK，TMS，TDI和TRST *信号的指令和数据同时汇总给所有系统逻辑板。 这四个信号由每个系统逻辑板通过由ME信号线控制的接口使能电路接收。 如果指令或数据是用于特定的系统逻辑板，则其对应的ME信号线将被使能以允许这些信号和所产生的TDO信号通过接口使能电路。 这种布置允许将总线TAP接口结合到系统控制接口中，用于测试和控制完全符合IEEE 1149.1标准的系统逻辑板，同时将专用于TAP信号的系统控​​制器卡背板引脚保留到每个系统逻辑的两个引脚 板上加上四个引脚，用于总线TAP接口。