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1.发明授权Prediffused integrated circuit and a method of interconnection of the cells of said circuit 失效预扩充集成电路和所述电路的单元的互连方法
公开(公告)号：US4644382A
公开(公告)日：1987-02-17
申请号：US820895
申请日：1986-01-17
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L27/092 , H01L27/118 , H01L29/78
CPC分类号： H01L27/11807 , H01L27/092
摘要： A prediffused integrated circuit having rows of basic cells on a substrate. Each basic cell includes two MOS transistors connected in series through a common drain or source electrode, each transistor having a separate gate. All basic cells in a row are the same type while adjacent rows alternate between p-type and n-type.
摘要翻译： 一种在基板上具有基本单元行的预扩充集成电路。 每个基本单元包括通过公共漏极或源极串联连接的两个MOS晶体管，每个晶体管具有单独的栅极。 一行中的所有基本单元格都是相同的类型，而相邻的行在p型和n型之间交替。
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公开(公告)号：US4074077A
公开(公告)日：1978-02-14
申请号：US684964
申请日：1976-05-10
申请人： Pierre Charransol , Jacques Hauri , Claude Athenes
发明人： Pierre Charransol , Jacques Hauri , Claude Athenes
CPC分类号： H04Q11/04
摘要： The invention relates to time-division exchanges in which the connection between the subscribers is established successively in time at the same frequency as a sampling of telephone signals. It consists in carrying out the spatial multiplex switching stage simultaneously on k words in series mode, each word using a separate spatial multiplex switch. A spatial multiplex switching stage with k independent elements is thus provided.This invention relates to time-division exchanges, in which the connection between the subscribers is established successively in time at the same rate as a sampling of telephone signals. The invention also relates to methods reshaping an exchange of this kind.These signals are generally sampled at a frequency of 8kc/s, after which the value of each sample is coded by a number of 8 bits. In most cases, this is followed by concentration which makes it possible, for example, to reduce the number of subscribers capable of being simultaneously connected from 256 to 32, the others awaiting a free connection. The degree of concentration is governed by the traffic expected on the subscriber lines which is known statistically. In general, the concentration circuit then delivers a frame of 32 channels multiplexed in time which is supported by a so-called multiplex junction circuit. It is also possible to carry out concentration with analogue samples, followed by encoding.The above mentioned numerical values are not critical, although they are generally used because of national and international standards.One significant problem is to guarantee adequate safety of operations in the event of failure of an element so that, instead of all the lines served by the automatic switching system having to be taken out of service, the blocking level is merely increased to a small extent.One solution to this problem is described in French Patent Application No. 75.05799. It comprises dividing shaping of an exchange of the type in question into n identical and independent sections connected at the level of the space-division switches by n busbars. Considering these spatial multiplex switches thus connected as a whole, it is apparent that they could be placed in the form of a matrix with n inputs and n outputs comprising n.sup.2 connection points.In the case of a high-capacity exchange this number of connection points would be too high. One known solution to this problem comprises using a multistage spatial multiplex switching network made up of a large number of matrices of small dimensions. Finally the number of connection points of these matrices as a whole is distinctly below n.sup.2, but it is no longer possible to return to the structure described above and the preceding protection system is no longer applicable.However, protection is essential, especially at the level of the spatial multiplex switch, because switching matrices are integrated in one and the same housing in which the failure of one element has consequential effects on all the others. Taking as an example a very simple integrated circuit comprising 4 multiplexers with 8 multiple inputs and used in the normal way in a connection network operating in parallel mode at a frequency of 2 MHz, this circuit will be used for more than 1000 calls. A failure of a circuit such as this is extremely serious.Various processes for replacing all or some of the safety elements of the switching network have already been proposed. These processes are attended by the disadvantage of requiring a large number of switches which, even if they are of the static type, may themselves be the origin of failures. In addition, the rescue switching procedure is complex and involves the loss of a large number of calls.In accordance with the present invention a time-division exchange is provided for switching binary words of k bits from a plurality of incoming parallel-mode PCM junctions to a plurality of output parallel-mode PCM junctions, said exchange comprising:first time-division switching means connected to said incoming PCM junctions for delivering said binary words in parallel mode;parallel-series conversion means for receiving said binary words from said first time-division switching means and delivering said binary words in series mode on k + n pluralities of input connections;matrix switching means connected to said k + n pluralities of input connections for delivering said binary words in series mode on k + n pluralities of output connections; said matrix switching means being divided into k + n independent distinct elements, each of said elements being connected respectively to one of said pluralities of input connections and to one of said pluralities of output connections and presenting to said binary words a plurality of paths between said input connections and said output connections;series-parallel conversion means connected to said k + n pluralities of output connections for delivering said binary words in parallel mode; andsecond time-division switching means connected to said series parallel conversion means for delivering said binary words to said plurality of output parallel-mode PCM junctions.
摘要翻译： 本发明涉及时分交换，其中用户之间的连接在时间上以与电话信号的采样相同的频率连续建立。 它包括在串行模式下在k个字上同时执行空间复用切换级，每个单词使用单独的空间复用开关。 因此提供了具有k个独立元件的空间多路复用切换级。
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公开(公告)号：US4224475A
公开(公告)日：1980-09-23
申请号：US4237
申请日：1979-01-17
申请人： Pierre Charransol , Claude Athenes , Jacques Salle
发明人： Pierre Charransol , Claude Athenes , Jacques Salle
CPC分类号： H04Q11/04
摘要： A switching system for telephone exchanges employing pulse code modulation (PCM). The time division switching network uses standard circuits of a single type, i.e., symmetrical time division matrices (MTS) and, in a particular embodiment, one PCM telephone junction is multipled onto two inputs of two MTSs and the latter are rejoined by two bi-directional junctions so that the construction of telephone exchange according to the invention permits simple and easy extensions of the capacity of the switching system.
摘要翻译： 一种采用脉码调制（PCM）的电话交换系统。 时分交换网络使用单一类型的标准电路，即对称时分矩阵（MTS），并且在特定实施例中，一个PCM电话连接被乘以两个MTS的两个输入，并且后者由两个双向 定向接点，使得根据本发明的电话交换机的构造允许简单和容易地扩展交换系统的容量。
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4.发明授权Symmetrical time division matrix and a network equipped with this kind of matrix 失效对称时分矩阵和配备这种矩阵的网络
公开(公告)号：US4093827A
公开(公告)日：1978-06-06
申请号：US768632
申请日：1977-02-14
申请人： Pierre Charransol , Jacques Hauri , Claude Athenes
发明人： Pierre Charransol , Jacques Hauri , Claude Athenes
CPC分类号： H04Q11/06
摘要： The invention relates to switching matrices used in exchanges of time-division kind and to networks using that kind of matrices. It consists in utilizing at the input and output of a symmetrical time matrix, a multiplexer and a demultiplexer which enable the overall circuit to address an arbitrary IT (time slot) of an arbitrary incoming junction, to an arbitrary IT on an arbitrary outgoing junction. A network using only that kind of matrices is disclosed.
摘要翻译： 本发明涉及使用时分类型交换的切换矩阵和使用该类矩阵的网络。 它包括在对称时间矩阵的输入和输出中使用多路复用器和解复用器，其使得整个电路能够将任意输入结的任意IT（时隙）寻址到任意输出结上的任意IT。 公开了仅使用那种类型的矩阵的网络。
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5.发明授权Switching network for establishing two-way connections between selected subscribers and an automatic exchange in a PCM telephone system 失效用于建立选定用户之间的双向连接和PCM电话系统中的自动交换的交换网络
公开(公告)号：US4154982A
公开(公告)日：1979-05-15
申请号：US849253
申请日：1977-11-07
申请人： Pierre Charransol , Jacques Hauri , Claude Athenes
发明人： Pierre Charransol , Jacques Hauri , Claude Athenes
CPC分类号： H04Q11/08
摘要： A switching network with k=p+q inputs and as many outputs comprises one or more symmetrical time-division matrices, k being eight or a multiple of eight in the embodiments specifically disclosed. A larger number p of incoming subscriber links and a smaller number q of exchange outputs are respectively connected to p outgoing subscriber links and q exchange inputs. Digitized voice samples arriving over each incoming link in successive time slots of a recurrent frame, allocated to respective subscribers, are stored in each matrix and are selectively distributed to the reduced number of time slots sent to the exchange under the control of switching instructions from the exchange; conversely, signal samples received from the exchange in successive time slots are distributed to selected time slots of outgoing links. Signal paths can also be established between network inputs and outputs connected to incoming and outgoing links, thereby enabling direct communication between subscribers served by the network.
摘要翻译： 具有k = p + q个输入和多个输出的交换网络包括一个或多个对称时分矩阵，在具体公开的实施例中，k为8或8的倍数。 较大数量的输入用户链路和较少数量的交换机输出分别连接到p个出站用户链路和q个交换输入。 分配给各个用户的经常性帧的连续时隙中的每个进入链路到达的数字化语音样本被存储在每个矩阵中，并且被选择性地分配给在交换指令的控制下发送到交换机的减少数量的时隙 交换; 相反，在连续时隙中从交换机接收的信号样本被分配到输出链路的选定时隙。 也可以在连接到输入和输出链路的网络输入和输出之间建立信号路径，从而实现由网络服务的用户之间的直接通信。
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公开(公告)号：US4142068A
公开(公告)日：1979-02-27
申请号：US807687
申请日：1977-06-17
申请人： Pierre Charransol , Jacques Hauri , Claude Athenes
发明人： Pierre Charransol , Jacques Hauri , Claude Athenes
CPC分类号： H04Q11/06
摘要： The invention relates to the connection networks used for switching digital signals, more especially telephonic PCM signals. It consists in organizing the spatial stage of a network of the TST type operating in series mode so as to divide into two the number of switching planes of that network. Each plane is with blocking although the assembly is without blocking. Moreover the number of time paths that enables the spatial stage to be traversed is doubled.
摘要翻译： 本发明涉及用于切换数字信号的连接网络，更特别地涉及电话PCM信号。 它包括组织以串联方式工作的TST型网络的空间级，以便将该网络的切换平面的数量分成两部分。 每个平面都有阻塞，尽管装配没有阻塞。 此外，使空间阶段能够遍历的时间路径的数量增加一倍。
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公开(公告)号：US4317008A
公开(公告)日：1982-02-23
申请号：US143555
申请日：1980-04-25
CPC分类号： H04Q11/04
摘要： The modular switching network for time-division telephone exchanges, which may be applied to small-capacity time-division telephone exchanges, is constituted by the direct connection of pairs of subscriber and trunk line connecting units by PCM digital trunks, each connecting unit comprising a concentration-deconcentrator device for serving the subscribers associated with this connecting unit.
摘要翻译： 可应用于小容量时分电话交换机的时分电话交换的模块化交换网络由PCM数字中继线直接连接用户和中继线连接单元，每个连接单元包括 集中分配器装置，用于服务与该连接单元相关联的用户。
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8.发明授权Method of synchronizing a pulse code modulation (PCM) junction and an arrangement for applying this method 失效同步脉冲编码调制（PCM）接口的方法和应用该方法的方案
公开(公告)号：US4095048A
公开(公告)日：1978-06-13
申请号：US696197
申请日：1976-06-15
申请人： Claude Athenes , Jean Pierre Landez
发明人： Claude Athenes , Jean Pierre Landez
CPC分类号： H04L25/05 , H04J3/0626 , H04Q11/04
摘要： The invention provides a method of synchronization of a junction in a pulse-code modulation (PCM) transmission network where any two multiplexing-demultiplexing stations equipped with independents clocks have to be brought into synchronism. For this purpose, the pulse trains (T.I.) of the PCM junction are alternatively recorded on two parallel channels A and B (registers RPA and RPB) and then memorized in a frame memory (MTR) by repeating the reading of the register when a risk of error is detected by comparison of the clocks. Means are provided for relocating the T.I. containing the multiframe locking code and the first frame of multiframe.
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公开(公告)号：US06584523B1
公开(公告)日：2003-06-24
申请号：US09478600
申请日：2000-01-06
IPC分类号： G06F1300
CPC分类号： G06F13/18
摘要： This invention relates to a device for organizing access to a bus connecting a memory to at least two entities asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.
摘要翻译： 本发明涉及一种用于组织对总线的访问的设备，该总线将存储器连接到表示对总线访问的请求的至少两个实体的异步二进制信号。 该设备提供二进制信号以根据不同请求之间的优先级确定授权对实体的访问，并且包括与输入寄存器相关联的有线逻辑中的优先级解码器。 当存储器的读或写周期执行时存在访问请求信号的状态的加载，当脉冲到由存储器关联的存储器控制器发出的信号和指示 的记忆周期结束。
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10.发明授权HDLC integrated circuit using internal arbitration to prioritize access to a shared internal bus amongst a plurality of devices 失效HDLC集成电路使用内部仲裁来优先访问多个设备之间的共享内部总线
公开(公告)号：US5878279A
公开(公告)日：1999-03-02
申请号：US690928
申请日：1996-08-01
申请人： Claude Athenes
发明人： Claude Athenes
摘要： This invention relates to an integrated HDLC circuit of the type including at least one HDLC controller and one DMA controller, and means for organizing the access to a first external bus for connection to an external memory, via an internal bus to which are connected different entities, which require to have access to the external memory, the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit.
摘要翻译： 本发明涉及一种包括至少一个HDLC控制器和一个DMA控制器的集成HDLC电路，以及用于经由连接到不同实体的内部总线来组织对第一外部总线的访问以连接到外部存储器的装置 ，其需要访问外部存储器，内部总线通过集成在HDLC电路中的存储器控制器连接到第一外部总线。
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