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公开(公告)号：US20220246204A1
公开(公告)日：2022-08-04
申请号：US17723358
申请日：2022-04-18
Inventor： Jinseok KIM , Yulhwa KIM , Jae-Joon KIM , Hyungjun KIM
IPC: G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US20210074349A1
公开(公告)日：2021-03-11
申请号：US17011929
申请日：2020-09-03
Inventor： Jinseok KIM , Yulhwa KIM , Jae-Joon KIM , Hyungjun KIM
IPC: G11C11/412 , G11C11/419 , G11C11/418 , G06N3/08
Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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