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公开(公告)号：US20210074349A1
公开(公告)日：2021-03-11
申请号：US17011929
申请日：2020-09-03
Inventor： Jinseok KIM , Yulhwa KIM , Jae-Joon KIM , Hyungjun KIM
IPC: G11C11/412 , G11C11/419 , G11C11/418 , G06N3/08
Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US20200160160A1
公开(公告)日：2020-05-21
申请号：US16687599
申请日：2019-11-18
Inventor： Jae-Joon KIM , Hyungjun KIM , Yulhwa KIM
Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.
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Patent Agency Ranking
3.发明公开公开(公告)号：US20230362498A1
公开(公告)日：2023-11-09
申请号：US18353801
申请日：2023-07-17
Inventor： Hyungjun KIM , Yulhwa KIM , Sungju RYU , Jae-Joon KIM
CPC classification number: H04N23/84 , G06T7/97 , G06T2207/20084 , G06T2207/20221
Abstract: An electronic system may include: a camera to capture a current image; an image processor to generate current image data items; and a splitter circuit to generate first and second images having respective first and second image data items. The splitter circuit splits each current image data item into a first image data item with a first set of bits and a second image data item with a second set of bits distinct from the first set of bits. The first and second image data items correspond to two distinct precisions less than a precision of the current image data items. The electronic system may also include distinct binary neural network circuits to independently process the first and second images to generate first and second processed image data items; and a merger circuit to combine the processed image data items to recover output image data items for display.
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公开(公告)号：US20210027142A1
公开(公告)日：2021-01-28
申请号：US16933889
申请日：2020-07-20
Inventor： Hyungjun KIM , Yulhwa KIM , Sungju RYU , Jae-Joon KIM
Abstract: Disclosed is a method of operating a neural network system. The method includes splitting input feature data into first splitting data corresponding to a first digit bit and second splitting data corresponding to a second digit bit different from the first digit bit, propagating the first splitting data through a first binary neural network, propagating the second splitting data through a second binary neural network, and merging first result data by propagation of the first splitting data and second result data by propagating the second splitting data to generate output feature data.
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公开(公告)号：US20220069821A1
公开(公告)日：2022-03-03
申请号：US17298917
申请日：2019-12-09
Inventor： Eun Hwan KIM , Jae-Joon KIM
IPC: H03K19/0944
Abstract: A pseudo-complementary logic network according to this embodiment includes a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes the second pull-down circuit.
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公开(公告)号：US20220246204A1
公开(公告)日：2022-08-04
申请号：US17723358
申请日：2022-04-18
Inventor： Jinseok KIM , Yulhwa KIM , Jae-Joon KIM , Hyungjun KIM
IPC: G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US20210303980A1
公开(公告)日：2021-09-30
申请号：US17108927
申请日：2020-12-01
Inventor： Sungju RYU , Jae-Joon KIM , Youngtaek OH
Abstract: A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.
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