公开(公告)号：US11367728B2

公开(公告)日：2022-06-21

申请号：US17075708

申请日：2020-10-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Hsiao-Pei Lin ,  Po-Yi Wu ,  Kuo-Fang Huang

IPC分类号： H01L27/108 ,  H01L49/02

摘要： Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

公开(公告)号：US20210043633A1

公开(公告)日：2021-02-11

申请号：US17075708

申请日：2020-10-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Hsiao-Pei Lin ,  Po-Yi Wu ,  Kuo-Fang Huang

IPC分类号： H01L27/108 ,  H01L49/02

摘要： Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

公开(公告)号：US20210035980A1

公开(公告)日：2021-02-04

申请号：US17075705

申请日：2020-10-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Hsiao-Pei Lin ,  Po-Yi Wu ,  Kuo-Fang Huang

IPC分类号： H01L27/108 ,  H01L49/02

摘要： Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

公开(公告)号：US11367727B2

公开(公告)日：2022-06-21

申请号：US17075705

申请日：2020-10-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Hsiao-Pei Lin ,  Po-Yi Wu ,  Kuo-Fang Huang

IPC分类号： H01L27/108 ,  H01L49/02

摘要： Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.