公开(公告)号：US20240162082A1

公开(公告)日：2024-05-16

申请号：US18150795

申请日：2023-01-06

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Ya-Ting Chen ,  Pin-Chieh Huang

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31144 ,  H01L23/481 ,  H01L24/80 ,  H01L21/76877 ,  H01L2224/80896

摘要： A manufacturing method of a semiconductor structure including following steps is provided. A first sacrificial layer and a second sacrificial layer are formed in a first substrate. A first device layer including a first dielectric structure and a first landing pad is formed on the first substrate. A second device layer including a second dielectric structure and a second landing pad is formed on a second substrate. The first dielectric structure is bonded to the second dielectric structure. A portion of the first substrate is removed to expose the first sacrificial layer and the second sacrificial layer. An etch-back process is performed by using the first substrate as a mask to form a first opening exposing the first landing pad and a second opening exposing the second landing pad. A first TSV structure and a second TSV structure are respectively formed in the first opening and the second opening.

公开(公告)号：US11367728B2

公开(公告)日：2022-06-21

申请号：US17075708

申请日：2020-10-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Hsiao-Pei Lin ,  Po-Yi Wu ,  Kuo-Fang Huang

IPC分类号： H01L27/108 ,  H01L49/02

摘要： Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

公开(公告)号：US12080590B2

公开(公告)日：2024-09-03

申请号：US17584385

申请日：2022-01-26

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Hung-Yao Huang ,  Shyng-Yeuan Che ,  Ching-Hsiu Wu

IPC分类号： H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76883

摘要： A manufacturing method of an interconnect structure including the following is provided. A substrate is provided. Sacrificial layers are formed on the substrate. A dielectric layer is formed between two adjacent sacrificial layers. There is an air gap in the dielectric layer. The sacrificial layers are removed to form first openings. A conductive layer is formed in the first opening.

公开(公告)号：US11152367B1

公开(公告)日：2021-10-19

申请号：US17008642

申请日：2020-09-01

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shyng-Yeuan Che ,  Shih-Ping Lee ,  Bo-An Tsai

IPC分类号： G11C11/4097 ,  H01L27/108

摘要： A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes first well regions and a second well region in a semiconductor substrate; first transistors within the first wells; second transistors within the second well; and bit lines. The first wells are separately arranged along a first direction and a second direction. The second well continuously spreads between the first wells. Each first transistor and one of the second transistors are adjacent and connected to each other via a common source or common drain. The common drain or common source is electrically connected to a storage capacitor, and the electrically connected first and second transistors as well as the storage capacitor form a memory cell. The bit lines respectively extend between adjacent rows of the first wells. Adjacent memory cells arranged along the second direction are electrically connected to the same bit line.

公开(公告)号：US11367727B2

公开(公告)日：2022-06-21

申请号：US17075705

申请日：2020-10-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Hsiao-Pei Lin ,  Po-Yi Wu ,  Kuo-Fang Huang

IPC分类号： H01L27/108 ,  H01L49/02

摘要： Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

公开(公告)号：US11069715B2

公开(公告)日：2021-07-20

申请号：US16285245

申请日：2019-02-26

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shyng-Yeuan Che ,  Shih-Ping Lee

IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L21/308 ,  H01L49/02 ,  H01L21/768 ,  H01L29/78

摘要： A memory structure including a SOI substrate, a first transistor, a second transistor, an isolation structure and a capacitor is provided. The SOI substrate includes a silicon base, a dielectric layer and a silicon layer. The first transistor and the second transistor are disposed on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is disposed between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the body portion, penetrates through the isolation structure and extends into the dielectric layer.

公开(公告)号：US20240113041A1

公开(公告)日：2024-04-04

申请号：US17978968

申请日：2022-11-02

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Bo-An Tsai ,  Shyng-Yeuan Che ,  Shih-Ping Lee

IPC分类号： H01L23/00 ,  G06F21/79

CPC分类号： H01L23/576 ,  G06F21/79

摘要： A physical unclonable function (PUF) generator structure including a substrate and a PUF generator is provided. The PUF generator includes a first electrode layer, a second electrode layer, a first dielectric layer, a first contact, a second contact, and a third contact. The first electrode layer is disposed on the substrate. The second electrode layer is disposed on the first electrode layer. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The first contact and the second contact are electrically connected to the first electrode layer and are separated from each other. The third contact is electrically connected to the second electrode layer.

公开(公告)号：US20230187272A1

公开(公告)日：2023-06-15

申请号：US17584385

申请日：2022-01-26

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Hung-Yao Huang ,  Shyng-Yeuan Che ,  Ching-Hsiu Wu

IPC分类号： H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76883

摘要： A manufacturing method of an interconnect structure including the following is provided. A substrate is provided. Sacrificial layers are formed on the substrate. A dielectric layer is formed between two adjacent sacrificial layers. There is an air gap in the dielectric layer. The sacrificial layers are removed to form first openings. A conductive layer is formed in the first opening.

公开(公告)号：US20210327879A1

公开(公告)日：2021-10-21

申请号：US17008642

申请日：2020-09-01

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shyng-Yeuan Che ,  Shih-Ping Lee ,  Bo-An Tsai

IPC分类号： H01L27/108 ,  G11C11/4097

摘要： A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes first well regions and a second well region in a semiconductor substrate; first transistors within the first wells; second transistors within the second well; and bit lines. The first wells are separately arranged along a first direction and a second direction. The second well continuously spreads between the first wells. Each first transistor and one of the second transistors are adjacent and connected to each other via a common source or common drain. The common drain or common source is electrically connected to a storage capacitor, and the electrically connected first and second transistors as well as the storage capacitor form a memory cell. The bit lines respectively extend between adjacent rows of the first wells. Adjacent memory cells arranged along the second direction are electrically connected to the same bit line.

公开(公告)号：US20210043633A1

公开(公告)日：2021-02-11

申请号：US17075708

申请日：2020-10-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Hsiao-Pei Lin ,  Po-Yi Wu ,  Kuo-Fang Huang

IPC分类号： H01L27/108 ,  H01L49/02

摘要： Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.