公开(公告)号：US20130311792A1

公开(公告)日：2013-11-21

申请号：US13474718

申请日：2012-05-18

申请人： Prahallada Ponnathota ,  Sean Fitzpatrick

发明人： Prahallada Ponnathota ,  Sean Fitzpatrick

IPC分类号： G06F1/26 ,  G05F1/10

CPC分类号： G06F1/26 ,  G06F1/3296 ,  Y02D10/172

摘要： The subject matter of this application is embodied in an apparatus that includes a data processor, and at least one hardware monitor to measure circuit delays associated with the data processor and a power supply to provide power to the data processor. The apparatus also includes a voltage regulator to regulate a voltage level provided by the power supply, and a look-up table having target voltage values and target circuit delay values each corresponding to one or more conditions. The apparatus further includes a controller to control the voltage regulator. The controller at various time points controls the voltage regulator based on target voltage values obtained from the look-up table. In between the time points, the controller controls the voltage regulator based on differences between target circuit delay values and measured circuit delay values.

摘要翻译： 该应用的主题体现在包括数据处理器和至少一个硬件监视器的装置中，该硬件监视器用于测量与数据处理器相关联的电路延迟和向数据处理器提供电力的电源。 该装置还包括用于调节由电源提供的电压电平的电压调节器和具有目标电压值和目标电路延迟值的查找表，每个对应于一个或多个条件。 该装置还包括控制电压调节器的控制器。 不同时间点的控制器基于从查找表获得的目标电压值来控制电压调节器。 在时间点之间，控制器根据目标电路延迟值和测量的电路延迟值之间的差异来控制电压调节器。

公开(公告)号：US08391267B2

公开(公告)日：2013-03-05

申请号：US12194521

申请日：2008-08-19

申请人： Prahallada Ponnathota ,  Thomas F. Howe

发明人： Prahallada Ponnathota ,  Thomas F. Howe

IPC分类号： H04J13/00

CPC分类号： H04L1/0043 ,  H04B1/707 ,  H04B2201/70707

摘要： A wireless system includes a TTI memory architecture in which encoded data are stored in a memory at a rate of one block of encoded data per transmission time interval (TTI), TTI being selected from a set of predetermined values, the memory including memory lines each having a predetermined number of bits that is determined according to the set of predetermined TTI values. For every block of data in which the end of the block of data does not align with an end of a last memory line occupied by the block of data, one or more padded bits are stored after the end of the block of data to the end of the last memory line occupied by the block of data so the last memory line is filled with a portion of the block of data and the one or more padded bits. The block of data and the padded bits are read in one or more equal sized segments.

摘要翻译： 无线系统包括TTI存储器架构，其中编码数据以每个传输时间间隔（TTI）的一个编码数据块的速率存储在存储器中，TTI从一组预定值中选择，存储器包括每个存储器线 具有根据预定TTI值的集合确定的预定数量的比特。 对于其中数据块的结尾与数据块占用的最后一个存储器行的结尾不对齐的每个数据块，在数据块结束之后存储一个或多个填充位到最后 由数据块占用的最后一条存储线，以便最后一条存储线被一部分数据块和一个或多个填充位填满。 数据块和填充位以一个或多个相等大小的段读取。

公开(公告)号：US08094641B2

公开(公告)日：2012-01-10

申请号：US12194516

申请日：2008-08-19

申请人： Deepak Mathew ,  Russ Mestechkin ,  Prahallada Ponnathota ,  Thomas F. Howe ,  Timothy Perrin Fisher-Jeffes

发明人： Deepak Mathew ,  Russ Mestechkin ,  Prahallada Ponnathota ,  Thomas F. Howe ,  Timothy Perrin Fisher-Jeffes

IPC分类号： H04B7/216

CPC分类号： H04B1/707 ,  G06F5/16 ,  G11C7/1075 ,  H04B2201/70707

摘要： A wireless device has a BRP-CRP interface that includes a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port. A bit rate processor performs bit rate processing on input data and writes data resulting from the bit rate processing to the dual-port frame memory through the first access port. A chip rate processor reads data from the dual-port frame memory through the second access port and performs chip rate processing on the data read from the dual-port frame memory. A data processor executes a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port.

摘要翻译： 无线设备具有BRP-CRP接口，其包括具有第一接入端口和第二接入端口的双端口帧存储器，其中可以通过第一接入端口将数据写入双端口帧存储器，同时该 通过第二个访问端口从双端口帧存储器中读取数据。 比特率处理器对输入数据执行比特率处理，并将通过比特率处理产生的数据通过第一接入端口写入双端口帧存储器。 芯片速率处理器通过第二访问端口从双端口帧存储器读取数据，并对从双端口帧存储器读取的数据执行码片速率处理。 数据处理器执行通过第一访问端口向双端口帧存储器写入数据的软件应用程序，并通过第二访问端口从双端口帧存储器读取数据。

公开(公告)号：US20090161649A1

公开(公告)日：2009-06-25

申请号：US12194521

申请日：2008-08-19

申请人： Prahallada Ponnathota ,  Thomas F. Howe

发明人： Prahallada Ponnathota ,  Thomas F. Howe

IPC分类号： H04J13/00

CPC分类号： H04L1/0043 ,  H04B1/707 ,  H04B2201/70707

摘要： A wireless system includes a TTI memory architecture in which encoded data are stored in a memory at a rate of one block of encoded data per transmission time interval (TTI), TTI being selected from a set of predetermined values, the memory including memory lines each having a predetermined number of bits that is determined according to the set of predetermined TTI values. For every block of data in which the end of the block of data does not align with an end of a last memory line occupied by the block of data, one or more padded bits are stored after the end of the block of data to the end of the last memory line occupied by the block of data so the last memory line is filled with a portion of the block of data and the one or more padded bits. The block of data and the padded bits are read in one or more equal sized segments.

摘要翻译： 无线系统包括TTI存储器架构，其中编码数据以每个传输时间间隔（TTI）的一个编码数据块的速率存储在存储器中，TTI从一组预定值中选择，存储器包括每个存储器线 具有根据预定TTI值的集合确定的预定数量的比特。 对于其中数据块的结尾与数据块占用的最后一个存储器行的结尾不对齐的每个数据块，在数据块结束之后存储一个或多个填充位到最后 由数据块占用的最后一条存储线，以便最后一条存储线被一部分数据块和一个或多个填充位填满。 数据块和填充位以一个或多个相等大小的段读取。