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    Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations
    1.
    发明授权
    Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations 有权
    同步数据处理系统，无论传播延迟和过程，电压和温度（PVT）变化如何，均可靠地传输数据

    公开(公告)号：US08355294B2

    公开(公告)日：2013-01-15

    申请号：US13050932

    申请日：2011-03-18

    申请人： Prakash Makwana ,  Prabhjot Singh

    发明人： Prakash Makwana ,  Prabhjot Singh

    IPC分类号： G11C8/18

    CPC分类号： G06F13/1689

    摘要： A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

    摘要翻译： 同步数据处理系统包括用于存储数据的存储器模块和耦合到存储器模块的存储器控​​制器。 存储器控制器包括时钟反相器，用于接收输入时钟信号并将反相时钟信号发送到存储器模块。 反向时钟信号在作为存储器时钟信号到达存储器模块之前引起第一传播延迟。 写数据缓冲器耦合到存储器模块。 写数据缓冲器响应于输入时钟信号将数据发送到存储器模块。 异步先入先出（ASYNC FIFO）缓冲器耦合到存储器模块。 响应于将存储器时钟信号反馈到ASYNC FIFO缓冲器而产生的反馈信号，ASYNC FIFO缓冲器从存储器模块读取数据。

    SYNCHRONOUS DATA PROCESSING SYSTEM AND METHOD
    2.
    发明申请
    SYNCHRONOUS DATA PROCESSING SYSTEM AND METHOD 有权
    同步数据处理系统和方法

    公开(公告)号：US20120239961A1

    公开(公告)日：2012-09-20

    申请号：US13050932

    申请日：2011-03-18

    申请人： Prakash Makwana ,  Prabhjot Singh

    发明人： Prakash Makwana ,  Prabhjot Singh

    IPC分类号： G06F1/12

    CPC分类号： G06F13/1689

    摘要： A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

    摘要翻译： 同步数据处理系统包括用于存储数据的存储器模块和耦合到存储器模块的存储器控​​制器。 存储器控制器包括时钟反相器，用于接收输入时钟信号并将反相时钟信号发送到存储器模块。 反向时钟信号在作为存储器时钟信号到达存储器模块之前引起第一传播延迟。 写数据缓冲器耦合到存储器模块。 写数据缓冲器响应于输入时钟信号将数据发送到存储器模块。 异步先入先出（ASYNC FIFO）缓冲器耦合到存储器模块。 ASYNC FIFO缓冲器响应于通过将存储器时钟信号反馈到ASYNC FIFO缓冲器而产生的反馈信号从存储器模块读取数据。