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    Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations
    1.
    发明授权
    Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations 有权
    同步数据处理系统，无论传播延迟和过程，电压和温度（PVT）变化如何，均可靠地传输数据

    公开(公告)号：US08355294B2

    公开(公告)日：2013-01-15

    申请号：US13050932

    申请日：2011-03-18

    申请人： Prakash Makwana ,  Prabhjot Singh

    发明人： Prakash Makwana ,  Prabhjot Singh

    IPC分类号： G11C8/18

    CPC分类号： G06F13/1689

    摘要： A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

    摘要翻译： 同步数据处理系统包括用于存储数据的存储器模块和耦合到存储器模块的存储器控​​制器。 存储器控制器包括时钟反相器，用于接收输入时钟信号并将反相时钟信号发送到存储器模块。 反向时钟信号在作为存储器时钟信号到达存储器模块之前引起第一传播延迟。 写数据缓冲器耦合到存储器模块。 写数据缓冲器响应于输入时钟信号将数据发送到存储器模块。 异步先入先出（ASYNC FIFO）缓冲器耦合到存储器模块。 响应于将存储器时钟信号反馈到ASYNC FIFO缓冲器而产生的反馈信号，ASYNC FIFO缓冲器从存储器模块读取数据。

    SYNCHRONOUS DATA PROCESSING SYSTEM AND METHOD
    2.
    发明申请
    SYNCHRONOUS DATA PROCESSING SYSTEM AND METHOD 有权
    同步数据处理系统和方法

    公开(公告)号：US20120239961A1

    公开(公告)日：2012-09-20

    申请号：US13050932

    申请日：2011-03-18

    申请人： Prakash Makwana ,  Prabhjot Singh

    发明人： Prakash Makwana ,  Prabhjot Singh

    IPC分类号： G06F1/12

    CPC分类号： G06F13/1689

    摘要： A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

    摘要翻译： 同步数据处理系统包括用于存储数据的存储器模块和耦合到存储器模块的存储器控​​制器。 存储器控制器包括时钟反相器，用于接收输入时钟信号并将反相时钟信号发送到存储器模块。 反向时钟信号在作为存储器时钟信号到达存储器模块之前引起第一传播延迟。 写数据缓冲器耦合到存储器模块。 写数据缓冲器响应于输入时钟信号将数据发送到存储器模块。 异步先入先出（ASYNC FIFO）缓冲器耦合到存储器模块。 ASYNC FIFO缓冲器响应于通过将存储器时钟信号反馈到ASYNC FIFO缓冲器而产生的反馈信号从存储器模块读取数据。

    Method and system for booting electronic device from NAND flash memory
    4.
    发明授权
    Method and system for booting electronic device from NAND flash memory 有权
    从NAND闪存启动电子设备的方法和系统

    公开(公告)号：US08990549B2

    公开(公告)日：2015-03-24

    申请号：US13547045

    申请日：2012-07-12

    申请人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

    发明人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4408

    摘要： A method and system for booting an electronic device from a NAND flash memory includes a NAND flash controller that receives an event trigger for fetching a pre-boot code stored in the NAND flash memory. Based on the event trigger type, booting parameters are loaded into the controller including a boot frequency of the NAND flash memory. The controller searches for a good memory block in which the pre-boot code is stored by checking the first and second or the first and last pages of a memory block and fetches a portion or the entire pre-boot code based on the event trigger type at the boot frequency.

    摘要翻译： 用于从NAND闪速存储器引导电子设备的方法和系统包括NAND闪存控制器，其接收用于获取存储在NAND闪速存储器中的预引导代码的事件触发。 基于事件触发类型，引导参数被加载到控制器中，包括NAND闪存的引导频率。 控制器通过检查存储器块的第一和第二或第一页和最后一页来搜索存储预引导代码的良好存储器块，并且基于事件触发类型获取部分或整个预引导代码 在引导频率。

    Method for Forming a Graded Matching Layer Structure
    5.
    发明申请
    Method for Forming a Graded Matching Layer Structure 审中-公开
    形成渐变匹配层结构的方法

    公开(公告)号：US20130195333A1

    公开(公告)日：2013-08-01

    申请号：US13362096

    申请日：2012-01-31

    申请人： Prabhjot Singh ,  Lowell Scott Smith

    发明人： Prabhjot Singh ,  Lowell Scott Smith

    IPC分类号： G06K9/00 ,  G10K11/00 ,  B05D5/12 ,  H01L41/04

    CPC分类号： G03F7/0035 ,  B06B1/0629 ,  H01L41/183

    摘要： A method for forming a graded matching layer structure is presented. The method includes (a) depositing a first material slurry on at least a portion of a substrate, (b) spreading the first material slurry to a form a first material layer having a first determined thickness, (c) exposing the first material layer using light processed through a determined light pattern mask to form a first matching layer, and (d) repeating steps (a)-(c) with different material slurries to form the graded matching layer structure.

    摘要翻译： 提出了一种形成渐变匹配层结构的方法。 该方法包括（a）在基底的至少一部分上沉积第一材料浆料，（b）将第一材料浆料铺展成具有第一确定厚度的第一材料层，（c）使用 通过确定的光图案掩模处理光以形成第一匹配层，以及（d）用不同的材料浆料重复步骤（a） - （c）以形成渐变匹配层结构。

    Multi-modality inspection system
    8.
    发明授权
    Multi-modality inspection system 有权
    多模态检查系统

    公开(公告)号：US07840367B2

    公开(公告)日：2010-11-23

    申请号：US11946244

    申请日：2007-11-28

    申请人： Francis Howard Little ,  Yanyan Wu ,  Prabhjot Singh

    发明人： Francis Howard Little ,  Yanyan Wu ,  Prabhjot Singh

    IPC分类号： G01B11/03 ,  G06F17/00

    CPC分类号： G01B11/03 ,  G01B5/008

    摘要： An inspection artifact includes a central portion and multiple optical and coordinate measurement machine (CMM) alignment features arranged on the central portion. The optical and CMM alignment features are configured to align the coordinates for an optical or a CMM measurement system to a common coordinate system. Another inspection artifact includes a central portion and multiple computed tomography (CT) alignment features arranged on the central portion. The CT alignment features are configured to align the coordinates for a CT system to a common coordinate system.

    摘要翻译： 检查工件包括中央部分和布置在中心部分上的多个光学和坐标测量机（CMM）对准特征。 光学和CMM对准特征被配置为将光学或CMM测量系统的坐标与公共坐标系对准。 另一种检查工件包括布置在中心部分上的中心部分和多个计算机断层摄影（CT）对准特征。 CT对准特征被配置为将CT系统的坐标与公共坐标系对齐。

    METHOD AND SYSTEM FOR BOOTING ELECTRONIC DEVICE FROM NAND FLASH MEMORY
    9.
    发明申请
    METHOD AND SYSTEM FOR BOOTING ELECTRONIC DEVICE FROM NAND FLASH MEMORY 有权
    用于从NAND闪存存储电子设备的方法和系统

    公开(公告)号：US20140019741A1

    公开(公告)日：2014-01-16

    申请号：US13547045

    申请日：2012-07-12

    申请人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

    发明人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

    IPC分类号： G06F9/445

    CPC分类号： G06F9/4408

    摘要： A method and system for booting an electronic device from a NAND flash memory includes a NAND flash controller that receives an event trigger for fetching a pre-boot code stored in the NAND flash memory. Based on the event trigger type, booting parameters are loaded into the controller including a boot frequency of the NAND flash memory. The controller searches for a good memory block in which the pre-boot code is stored by checking the first and second or the first and last pages of a memory block and fetches a portion or the entire pre-boot code based on the event trigger type at the boot frequency.

    摘要翻译： 用于从NAND闪速存储器引导电子设备的方法和系统包括NAND闪存控制器，其接收用于获取存储在NAND闪速存储器中的预引导代码的事件触发。 基于事件触发类型，引导参数被加载到控制器中，包括NAND闪存的引导频率。 控制器通过检查存储器块的第一和第二或第一页和最后一页来搜索存储预引导代码的良好存储器块，并且基于事件触发类型获取部分或整个预引导代码 在引导频率。

    DIRECT WRITING OF FUNCTIONALIZED ACOUSTIC BACKING
    10.
    发明申请
    DIRECT WRITING OF FUNCTIONALIZED ACOUSTIC BACKING 有权
    功能性声学背景的直接书写

    公开(公告)号：US20130088122A1

    公开(公告)日：2013-04-11

    申请号：US13267610

    申请日：2011-10-06

    申请人： Matthew Harvey Krohn ,  Prabhjot Singh

    发明人： Matthew Harvey Krohn ,  Prabhjot Singh

    IPC分类号： H01L41/053 ,  H04R31/00

    CPC分类号： B06B1/0629 ,  B06B1/0685 ,  B33Y10/00 ,  B33Y80/00 ,  H04R17/00 ,  H04R31/00 ,  Y10T29/49005

    摘要： An acoustic transducer and method of making the acoustic transducer is disclosed. A transducer element for converting a signal between one of an electrical signal and an acoustic signal and the other of the electrical signal and the acoustic signal is provided. A backing to the transducer is additively fabricated to a side of the transducer element. The backing includes an electrically conductive path therein for conducting the electrical signal.

    摘要翻译： 公开了一种声换能器和制造声换能器的方法。 提供了用于转换电信号和声信号之一以及电信号和声信号中的另一个的信号的换能器元件。 传感器的背面被附加地制造到换能器元件的一侧。 背衬包括用于传导电信号的导电路径。