公开(公告)号：US20020016035A1

公开(公告)日：2002-02-07

申请号：US09816356

申请日：2001-03-26

Applicant: ProMOS Technologies, Inc.

Inventor： Chao-Chueh Wu ,  Sheng-Fen Chiu ,  Jesse Chung ,  Hsiao-Lei Wang

IPC: H01L021/8242 ,  H01L021/20

CPC classification number: H01L27/1087

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad Si3N4 uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract translation: 实现了一种用于在晶片边缘处制造具有减小的沟槽刻面的DRAM电路的改进的深沟槽电容器的方法，并且改善了焊盘Si3N4均匀性以提高工艺产量。 该方法利用较厚的焊盘Si 3 N 4作为用于蚀刻深沟槽的硬掩模的一部分。 然后，在通过一系列工艺步骤形成深沟槽电容器之后，形成浅沟槽隔离（STI）。 该方法利用在较厚的焊盘Si3N4层中蚀刻浅沟槽并进入硅衬底。 将第二绝缘层沉积并抛光（CMP）到焊盘Si3N4层中。 一个关键特征是使用第二掩模来保护衬底中心，同时部分地蚀刻由固化地由CMP产生的衬底边缘处的衬垫Si3N4层的较厚部分。 这使焊盘Si3N4层的不均匀性最小化，以提供用于进一步处理的更可靠的结构。