公开(公告)号：US10073733B1

公开(公告)日：2018-09-11

申请号：US15693661

申请日：2017-09-01

Applicant: Purdue Research Foundation

Inventor： Shubham Jain ,  Ashish Ranjan ,  Kaushik Roy ,  Anand Raghunathan

IPC: G11C11/00 ,  G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/108

Abstract: A memory capable of carrying out compute-in-memory (CiM) operations is disclosed. The memory includes a matrix of bit cells having a plurality of bit cells along one or more rows and a plurality of bit cells along one or more columns, each bit cell having a value stored therein, an address decoder configured to receive addresses and activate two or more of the rows associated with the addresses, and a sensing circuit coupled to each column of bit cells, and configured to provide two or more outputs, wherein each output is associated with at least one compute operation performed on values stored in the bit cells in the column.

公开(公告)号：US20210089272A1

公开(公告)日：2021-03-25

申请号：US16581965

申请日：2019-09-25

Applicant: Purdue Research Foundation

Inventor： Shubham Jain ,  Anand Raghunathan ,  Sumeet Kumar Gupta

IPC: G06F7/523 ,  G11C11/412 ,  G11C11/419 ,  G11C11/418 ,  G06F17/16 ,  G06N3/063

Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.

公开(公告)号：US11966714B2

公开(公告)日：2024-04-23

申请号：US17588311

申请日：2022-01-30

Applicant: Purdue Research Foundation

Inventor： Shubham Jain ,  Anand Raghunathan ,  Sumeet Kumar Gupta

IPC: G11C11/412 ,  G06F7/523 ,  G06F17/16 ,  G06N3/063 ,  G11C11/418 ,  G11C11/419 ,  G11C15/04

CPC classification number: G06F7/523 ,  G06F17/16 ,  G06N3/063 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C15/04

Abstract: A circuit of cells used as a memory array and capable of in-memory arithmetic which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.

公开(公告)号：US20220206751A1

公开(公告)日：2022-06-30

申请号：US17588311

申请日：2022-01-30

Applicant: Purdue Research Foundation

Inventor： Shubham Jain ,  Anand Raghunathan ,  Sumeet Kumar Gupta

IPC: G06F7/523 ,  G11C11/412 ,  G06N3/063 ,  G11C11/418 ,  G06F17/16 ,  G11C11/419

Abstract: A circuit of cells used as a memory array and capable of in-memory arithmetic is disclosed which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.

公开(公告)号：US11281429B2

公开(公告)日：2022-03-22

申请号：US16581965

申请日：2019-09-25

Applicant: Purdue Research Foundation

Inventor： Shubham Jain ,  Anand Raghunathan ,  Sumeet Kumar Gupta

IPC: G11C11/412 ,  G06F7/523 ,  G06N3/063 ,  G11C11/418 ,  G06F17/16 ,  G11C11/419 ,  G11C15/04

Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.