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    OPTIMIZING SPOOL AND MEMORY SPACE MANAGEMENT
    1.
    发明申请
    OPTIMIZING SPOOL AND MEMORY SPACE MANAGEMENT 有权

    公开(公告)号：US20220300413A1

    公开(公告)日：2022-09-22

    申请号：US17831295

    申请日：2022-06-02

    Applicant: Pure Storage, Inc.

    Inventor： Hari Kannan ,  Ying Gao ,  Boris Feigin

    IPC: G06F12/02 ,  G06F3/06 ,  G06F11/30

    Abstract: A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.

    OPTIMIZING RESILIENCY GROUP FORMATION STABILITY
    3.
    发明申请
    OPTIMIZING RESILIENCY GROUP FORMATION STABILITY 有权

    公开(公告)号：US20220011955A1

    公开(公告)日：2022-01-13

    申请号：US17486084

    申请日：2021-09-27

    Applicant: PURE STORAGE, INC.

    Inventor： Ian Juch ,  Haijie Xiao ,  Hao Liu ,  Boris Feigin

    IPC: G06F3/06

    Abstract: A storage system determines a change in storage system geometry that affects at least one previously formed resiliency group of storage system resources. The storage system forms at least one resiliency group of storage system resources in accordance with rules that emphasize stability of formation of resiliency groups. The storage system accesses data stripes across storage system resources of resiliency groups.

    Resiliency groups
    4.
    发明授权
    Resiliency groups 有权

    公开(公告)号：US11138103B1

    公开(公告)日：2021-10-05

    申请号：US15965165

    申请日：2018-04-27

    Applicant: Pure Storage, Inc.

    Inventor： Guangyu Shi ,  Faissal Sleiman ,  Janis Stipins ,  Ying Gao ,  Matthew D. Fleming ,  Boris Feigin

    IPC: G06F16/11 ,  G06F12/02 ,  G06F3/06

    Abstract: A method of operating a plurality of blades of a storage system, performed by the storage system, is provided. The method includes writing data stripes across one or more sets of blades of the plurality of blades within resiliency groups, the plurality of blades having computing resources and storage memory, each resiliency group supporting data recovery in case of loss of a specified number of blades of the resiliency group. The method includes transferring data from a first resiliency group to a second resiliency group, responsive to a change in geometry of the storage system.

    Adaptive data migration
    5.
    发明授权
    Adaptive data migration 有权

    公开(公告)号：US11030090B2

    公开(公告)日：2021-06-08

    申请号：US16524491

    申请日：2019-07-29

    Applicant: Pure Storage, Inc.

    Inventor： Robert Lee ,  Svitlana Tumanova ,  Boris Feigin ,  Taher Vohra

    IPC: G06F3/06 ,  G06F12/02 ,  G06F11/30

    Abstract: A method for elective garbage collection in storage memory, performed by a storage system is provided. The method includes monitoring storage space available in each of a plurality of portions of storage memory of a storage system and detecting an imbalance in the storage space available across the plurality of portions of storage memory. The method includes performing garbage collection to rebalance the space available across the plurality of portions of storage memory, responsive to the detecting. A storage system is also provided.

    Dynamic buffer for storage system
    8.
    发明授权
    Dynamic buffer for storage system 有权

    公开(公告)号：US12229437B2

    公开(公告)日：2025-02-18

    申请号：US17832309

    申请日：2022-06-03

    Applicant: PURE STORAGE, INC.

    Inventor： Ying Gao ,  Boris Feigin ,  Hari Kannan

    IPC: G06F3/06

    Abstract: A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes determining that a size of a buffer of a storage system should be adjusted. The storage system comprises a non-volatile random-access memory (NVRAM), single level cell (SLC) flash memory, and quad level cell (QLC) flash memory. The buffer of the storage system comprises one or more of the NVRAM and a portion of the SLC flash memory. The method also includes adjusting the size of the buffer of the storage system to a first size.

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