公开(公告)号：US20150046732A1

公开(公告)日：2015-02-12

申请号：US13962746

申请日：2013-08-08

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER CHUN ,  YANRU LI ,  ALEX TU ,  MICHAEL LO

IPC: G06F1/32 ,  G11C14/00 ,  G06F12/06

CPC classification number: G06F1/3275 ,  G06F12/0607 ,  G06F2212/1028 ,  G11C14/0009 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.

Abstract translation: 公开了用于提供具有选择性功率或性能优化的存储器通道交织的系统和方法。 一种这样的方法涉及为经由具有交织区域和线性区域的两个或多个相应存储器通道访问的两个或多个存储器件配置存储器地址映射。 交织区域包括用于相对较高性能使用情况的交织地址空间。 线性区域包括用于相对较低功率使用情况的线性地址空间。 从一个或多个客户端收到内存请求。 存储器请求包括对节能或性能的偏好。 根据对功率节省或性能的偏好，接收到的存储器请求被分配给线性区域或交织区域。