公开(公告)号：US09501332B2

公开(公告)日：2016-11-22

申请号：US13721229

申请日：2012-12-20

Applicant: QUALCOMM Incorporated

Inventor： Dana M. Vantrease ,  Christopher E. Koob ,  Erich J. Plondke

IPC: G06F9/52 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0864 ,  G06F2212/6082 ,  Y02D10/13

Abstract: An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.

Abstract translation: 一种装置包括第一核心处理器，第二核心处理器和耦合到第一核心处理器和第二核心处理器的锁定寄存器。 该装置还包括响应于第一核心处理器和第二核心处理器的共享结构。 共享结构响应于由第一核心处理器或第二核心处理器发出的解锁指令，以向锁定寄存器发送信号以重置锁定寄存器中的锁定指示。

公开(公告)号：US20140181341A1

公开(公告)日：2014-06-26

申请号：US13721229

申请日：2012-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： Dana M. Vantrease ,  Christopher E. Koob ,  Erich J. Plondke

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0864 ,  G06F2212/6082 ,  Y02D10/13

Abstract: An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.

Abstract translation: 一种装置包括耦合到第一核心处理器和第二核心处理器的第一核心处理器，第二核心处理器和锁定寄存器。 该装置还包括响应于第一核心处理器和第二核心处理器的共享结构。 共享结构响应于由第一核心处理器或第二核心处理器发出的解锁指令，以向锁定寄存器发送信号以重置锁定寄存器中的锁定指示。