公开(公告)号：US20140181341A1

公开(公告)日：2014-06-26

申请号：US13721229

申请日：2012-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： Dana M. Vantrease ,  Christopher E. Koob ,  Erich J. Plondke

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0864 ,  G06F2212/6082 ,  Y02D10/13

Abstract: An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.

Abstract translation: 一种装置包括耦合到第一核心处理器和第二核心处理器的第一核心处理器，第二核心处理器和锁定寄存器。 该装置还包括响应于第一核心处理器和第二核心处理器的共享结构。 共享结构响应于由第一核心处理器或第二核心处理器发出的解锁指令，以向锁定寄存器发送信号以重置锁定寄存器中的锁定指示。

公开(公告)号：US09501332B2

公开(公告)日：2016-11-22

申请号：US13721229

申请日：2012-12-20

Applicant: QUALCOMM Incorporated

Inventor： Dana M. Vantrease ,  Christopher E. Koob ,  Erich J. Plondke

IPC: G06F9/52 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0864 ,  G06F2212/6082 ,  Y02D10/13

Abstract: An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.

Abstract translation: 一种装置包括第一核心处理器，第二核心处理器和耦合到第一核心处理器和第二核心处理器的锁定寄存器。 该装置还包括响应于第一核心处理器和第二核心处理器的共享结构。 共享结构响应于由第一核心处理器或第二核心处理器发出的解锁指令，以向锁定寄存器发送信号以重置锁定寄存器中的锁定指示。

公开(公告)号：US09142268B2

公开(公告)日：2015-09-22

申请号：US13719881

申请日：2012-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jentsung Lin ,  Paul D. Bassett ,  Manojkumar Pyla ,  Robert A. Lester ,  Christopher E. Koob

IPC: G11C7/00 ,  G11C7/10 ,  G06F5/10

CPC classification number: G11C7/1084 ,  G06F5/10

Abstract: Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.

Abstract translation: 公开了双电压域内存缓冲器以及相关的系统和方法。 为了减小用于电压电平移位的电压电平移位器所需的面积，锁存器组被提供在存储缓冲器读取电路的电压域中，与写入数据输入到锁存器组的电压域分开。 写入数据输入电压电平移位器设置在写入数据输入和锁存器组之间，以输入到锁存器组的电压域的写入数据上的电压电平移位写入数据。 以这种方式，由于锁存器组处于存储器缓冲器读取电路的电压域中，电压电平移位器不需要电压电平降低锁存器组输出。 以这种方式，不需要将电压电平移位器需要的电压电平移位锁存器组输出的半导体区域。

公开(公告)号：US20130182515A1

公开(公告)日：2013-07-18

申请号：US13719881

申请日：2012-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jentsung Lin ,  Paul D. Bassett ,  Manojkumar Pyla ,  Robert A. Lester ,  Christopher E. Koob

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G06F5/10

Abstract: Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.

Abstract translation: 公开了双电压域内存缓冲器以及相关的系统和方法。 为了减小用于电压电平移位的电压电平移位器所需的面积，锁存器组被提供在存储缓冲器读取电路的电压域中，与写入数据输入到锁存器组的电压域分开。 写入数据输入电压电平移位器设置在写入数据输入和锁存器组之间，以输入到锁存器组的电压域的写入数据上的电压电平移位写入数据。 以这种方式，由于锁存器组处于存储器缓冲器读取电路的电压域中，电压电平移位器不需要电压电平降低锁存器组输出。 以这种方式，不需要将电压电平移位器需要的电压电平移位锁存器组输出的半导体区域。