公开(公告)号：US11614941B2

公开(公告)日：2023-03-28

申请号：US15942344

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Amrit Panda ,  Francisco Perez ,  Karamvir Chatha

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/38 ,  G06N3/063

Abstract: An apparatus for hardware acceleration for use in operating a computational network is configured for determining that a loop structure including one or more loops is to be executed by a first processor. Each of the one or more loops includes a set of operations. The loop structure may be configured as a nested loop, a cascaded or a combination of the two. A second processor may be configured to decouple overhead operations of the loop structure from compute operations of the loop structure. The apparatus accelerates processing of the loop structure by simultaneously processing the overhead operations using the second processor separately from processing the compute operations based on the configuration to operate the computational network.

公开(公告)号：US11029745B2

公开(公告)日：2021-06-08

申请号：US16184934

申请日：2018-11-08

Applicant: QUALCOMM INCORPORATED

Inventor： Kyle Ernewein ,  Jason Edward Podaima ,  Francisco Perez ,  John Daniels ,  Alex Miler ,  Jeffrey Gemar ,  Rexford Alan Hill ,  Haoping Xu

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3228

Abstract: Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.