公开(公告)号：US20240386980A1

公开(公告)日：2024-11-21

申请号：US18522098

申请日：2023-11-28

Applicant: QUALCOMM Incorporated

Inventor： Simon Peter William BOOTH ,  Subbarao PALACHARLA ,  George PATSILARAS ,  Hiral NANDU ,  Girish BHAT ,  Yen-Kuan WU

IPC: G11C29/12

Abstract: Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may obtain an indication of a data write for data associated with data processing. The apparatus may write, based on the indication, the data associated with the data processing to a memory address. The apparatus may receive a read request for the data including the memory address, where the read request is associated with a read with invalidate process. The apparatus may retrieve, based on the read request, the data from at least one of a first cache or at least one second memory, where the retrieval of the data is based on a timing of the indication of the data write. The apparatus may output the retrieved data from at least one of the first cache or the at least one second memory.

公开(公告)号：US20230214330A1

公开(公告)日：2023-07-06

申请号：US17646690

申请日：2021-12-31

Applicant: QUALCOMM Incorporated

Inventor： Hiral NANDU ,  Subbarao PALACHARLA ,  George PATSILARAS ,  Alain ARTIERI ,  Simon Peter William BOOTH ,  Vipul GANDHI ,  Girish BHAT ,  Yen-Kuan WU ,  Younghoon KIM

IPC: G06F12/123 ,  G06F9/30

CPC classification number: G06F12/123 ,  G06F9/30101

Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

公开(公告)号：US20210397714A1

公开(公告)日：2021-12-23

申请号：US16903982

申请日：2020-06-17

Applicant: QUALCOMM INCORPORATED

Inventor： Steven HALTER ,  Samar ASBE ,  Miguel BALLESTEROS ,  Girish BHAT ,  Mahadevamurty NEMANI

IPC: G06F21/57 ,  G06F9/445 ,  G06F9/50 ,  G06F21/62

Abstract: Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.

公开(公告)号：US20210365557A1

公开(公告)日：2021-11-25

申请号：US16880819

申请日：2020-05-21

Applicant: QUALCOMM Incorporated

Inventor： Jaydeep CHOKSHI ,  Miguel BALLESTEROS ,  Mahadevamurty NEMANI ,  Samar ASBE ,  Girish BHAT ,  Alan YOUNG ,  Victor WONG ,  Steven HALTER

IPC: G06F21/57 ,  G06F21/44 ,  G06F11/36 ,  G06F13/42

Abstract: A method for external access control to protect system-on-chip (SoC) subsystems and stored subsystem assets is described. The method includes sensing, during a cold boot of an SoC hardware system, a debug fuse vector for access to SoC subsystems of an SoC owner and/or third-party subsystems of an SoC hardware architecture. The method also includes disabling access to each SoC subsystem with a blown fuse in the debug fuse vector. The method further includes re-enabling, by a secure root of trust, access to an SoC subsystem and/or a third-party subsystem for an external debugger when authentication of one or more debug certificates of a third-party owner of the external debugger is successful.

公开(公告)号：US20150079909A1

公开(公告)日：2015-03-19

申请号：US14302301

申请日：2014-06-11

Applicant: QUALCOMM Incorporated

Inventor： Carlos SOLEDADE ,  Ajay BAWALE ,  Graham ROFF ,  Girish BHAT

IPC: H04B15/02

CPC classification number: H04B15/02

Abstract: In one configuration, an apparatus and a method to operate the apparatus are provided. The apparatus includes at least one processor configured to receive operating information indicating a set of operating frequencies from a first circuit and to select an operating frequency from the set of operating frequencies. The at least one processor is further arranged to configure an operation of a second circuit based on the selected operating frequency. In another configuration, the apparatus includes at least one processor configured to select a set of operating frequencies based a radio frequency operation and to transmit operating information indicating the set of operating frequencies to a control circuit.

Abstract translation: 在一种配置中，提供了一种操作该装置的装置和方法。 该装置包括至少一个处理器，其被配置为从第一电路接收指示一组工作频率的操作信息，并从该组工作频率中选择一个工作频率。 所述至少一个处理器还被布置为基于所选择的操作频率来配置第二电路的操作。 在另一种配置中，该设备包括至少一个处理器，其被配置为基于射频操作来选择一组工作频率，并将指示该组工作频率的操作信息发送到控制电路。