公开(公告)号：US20240038672A1

公开(公告)日：2024-02-01

申请号：US17877156

申请日：2022-07-29

Applicant: QUALCOMM Incorporated

Inventor： Mahalingam NAGARAJAN ,  Vaishnav SRINIVAS ,  Nitin JUNEJA ,  Christophe AVOINNE ,  Xavier Loic LELOUP ,  Michael David JAGER ,  Charles David PAYNTER ,  Joon Young PARK

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/14132 ,  H01L24/81 ,  H01L2224/81815

Abstract: A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

公开(公告)号：US20230154502A1

公开(公告)日：2023-05-18

申请号：US18150155

申请日：2023-01-04

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Joon Young PARK ,  Mahalingam NAGARAJAN

IPC: G11C5/14 ,  H03K7/02

CPC classification number: G11C5/147 ,  H03K7/02

Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

公开(公告)号：US20210233579A1

公开(公告)日：2021-07-29

申请号：US16752442

申请日：2020-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： FARRUKH AQUIL ,  Vaishnav SRINIVAS ,  Mahalingam NAGARAJAN ,  Yong XU

IPC: G11C11/4076 ,  G06F13/42 ,  G11C11/409 ,  G11C7/10

Abstract: Signal timing drift in a synchronous dynamic random access memory (SDRAM) system may be compensated for by performing write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read at periodic intervals interspersed with mission-mode SDRAM traffic. The test result samples obtained from the write signal timing training may be analyzed independently of mission-mode SDRAM traffic. The mission-mode timing of the SDRAM data bit signals relative to the SDRAM write clock signal may be adjusted based on the analysis.