公开(公告)号：US20240273036A1

公开(公告)日：2024-08-15

申请号：US18626506

申请日：2024-04-04

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Conrado Blasco ,  Paul Kitchin ,  Huzefa Sanjeliwala

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583

Abstract: Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer comprising a plurality of TLB metadata buffer entries storing corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for use in accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request comprising a virtual address (VA), the MMU generates a TLB entry in the TLB for the VA, and stores the active TLB metadata pointer as part of the TLB tag of the TLB entry in lieu of the TLB metadata of the TLB metadata buffer entry.

公开(公告)号：US20240320157A1

公开(公告)日：2024-09-26

申请号：US18188200

申请日：2023-03-22

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Paul Kitchin ,  Huzefa Sanjeliwala

IPC: G06F12/0891 ,  G06F12/1027

CPC classification number: G06F12/0891 ,  G06F12/1027

Abstract: Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides a plurality of processors including an issuing processor and a remote processor. The remote processor receives, from the issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies filtering criteria, which specify conditions under which execution of the DSB instruction by the remote processor is unnecessary. If the remote processor determines that the TLBI instruction satisfies the filtering criteria, the remote processor foregoes execution of a DSB operation corresponding to the DSB instruction, and issues an early DSB acknowledgement to the issuing processor.

公开(公告)号：US12130751B2

公开(公告)日：2024-10-29

申请号：US18168871

申请日：2023-02-14

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Conrado Blasco ,  Paul Kitchin ,  Huzefa Sanjeliwala

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583

Abstract: Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer comprising a plurality of TLB metadata buffer entries storing corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for use in accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request comprising a virtual address (VA), the MMU generates a TLB entry in the TLB for the VA, and stores the active TLB metadata pointer as part of the TLB tag of the TLB entry in lieu of the TLB metadata of the TLB metadata buffer entry.

公开(公告)号：US20240273035A1

公开(公告)日：2024-08-15

申请号：US18623242

申请日：2024-04-01

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Sushmitha Ayyanar ,  Conrado Blasco

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/1016

Abstract: Exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a TLB, comprising multiple TLB entries each comprising a tag and a plurality of data portions, and further comprises a memory management unit (MMU). The MMU is configured to receive a memory access request comprising a VA, and determine that a TLB access to the TLB for a page VA of the VA results in a miss. In response, the MMU generates a TLB entry, wherein the tag of the TLB entry comprises the page VA, the plurality of data portions comprises a corresponding plurality of page PAs, a first data portion thereof comprising a page PA corresponding to the page VA, and one or more second data portions thereof comprising corresponding PAs of next sequential page VAs following the page VA.

公开(公告)号：US20240273033A1

公开(公告)日：2024-08-15

申请号：US18168857

申请日：2023-02-14

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Sushmitha Ayyanar ,  Conrado Blasco

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/1016

Abstract: Exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a TLB, comprising multiple TLB entries each comprising a tag and a plurality of data portions, and further comprises a memory management unit (MMU). The MMU is configured to receive a memory access request comprising a VA, and determine that a TLB access to the TLB for a page VA of the VA results in a miss. In response, the MMU generates a TLB entry, wherein the tag of the TLB entry comprises the page VA, the plurality of data portions comprises a corresponding plurality of page PAs, a first data portion thereof comprising a page PA corresponding to the page VA, and one or more second data portions thereof comprising corresponding PAs of next sequential page VAs following the page VA.

公开(公告)号：US20240320160A1

公开(公告)日：2024-09-26

申请号：US18623171

申请日：2024-04-01

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Paul Kitchin ,  Huzefa Sanjeliwala

IPC: G06F12/0891 ,  G06F12/1027

CPC classification number: G06F12/0891 ,  G06F12/1027

Abstract: Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides a plurality of processors including an issuing processor and a remote processor. The remote processor receives, from the issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies filtering criteria, which specify conditions under which execution of the DSB instruction by the remote processor is unnecessary. If the remote processor determines that the TLBI instruction satisfies the filtering criteria, the remote processor foregoes execution of a DSB operation corresponding to the DSB instruction, and issues an early DSB acknowledgement to the issuing processor.

公开(公告)号：US20240273034A1

公开(公告)日：2024-08-15

申请号：US18168871

申请日：2023-02-14

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Conrado Blasco ,  Paul Kitchin ,  Huzefa Sanjeliwala

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583

Abstract: Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer comprising a plurality of TLB metadata buffer entries storing corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for use in accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request comprising a virtual address (VA), the MMU generates a TLB entry in the TLB for the VA, and stores the active TLB metadata pointer as part of the TLB tag of the TLB entry in lieu of the TLB metadata of the TLB metadata buffer entry.

公开(公告)号：US12135652B2

公开(公告)日：2024-11-05

申请号：US18188200

申请日：2023-03-22

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Paul Kitchin ,  Huzefa Sanjeliwala

IPC: G06F12/0891 ,  G06F12/1027

Abstract: Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides a plurality of processors including an issuing processor and a remote processor. The remote processor receives, from the issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies filtering criteria, which specify conditions under which execution of the DSB instruction by the remote processor is unnecessary. If the remote processor determines that the TLBI instruction satisfies the filtering criteria, the remote processor foregoes execution of a DSB operation corresponding to the DSB instruction, and issues an early DSB acknowledgement to the issuing processor.

公开(公告)号：US11914524B2

公开(公告)日：2024-02-27

申请号：US17684231

申请日：2022-03-01

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Huzefa Sanjeliwala ,  Paul Kitchin ,  Prarthna Santhanakrishnan ,  Conrado Blasco ,  Pradeep Kanapathipillai

IPC: G06F12/1036 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F12/1036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/45558 ,  G06F2009/45562

Abstract: An electronic device includes one or more processors for executing one or more virtual machines. In response to a request for initiating a synchronization event, a processor identifies a subset of speculative memory access requests in one or more memory access request queues. Automatically and in accordance with the identifying, the processor purges translations associated with the subset of speculative memory access requests. Subsequent to the purging, the processor initiates the synchronization event. In some implementations, memory access completion is forced in response to a context synchronization event that corresponds to a termination of a first application, a termination of a first virtual machine, or a system call for updating a system register. Alternatively, in some implementations, memory access completion is forced in an operating system level or an application level in response to a data synchronization event that is initiated on a hypervisor layer or a firmware layer.