公开(公告)号：US20250070954A1

公开(公告)日：2025-02-27

申请号：US18455999

申请日：2023-08-25

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet DEY ,  Suresh VANKADARA ,  Alok KEDIYA ,  Ravikishore PAMPANA ,  Trishansh BHARDWAJ

IPC: H04L7/00 ,  H04N23/66

Abstract: Aspects of the disclosure are directed to self-synchronization of information data. In accordance with one aspect, an apparatus includes a receive physical (RX PHY) layer interface configured to send information data to a packet switch configured to suspend transmission of information data prior to arrival of a start of transaction (SOT) field and to commence transmission of information data upon arrival of the SOT field. The apparatus further includes a camera serial interface decoder (CSID) configured to receive information data from the packet switch; a frame switch configured to receive a start of frame (SOF) field from the CSID; an image signal processor (ISP) configured to receive decoded information data from the frame switch and to process decoded information data to generate a processed information data in a format compatible with an image display device; and a software module configured to enable the frame switch and the packet switch.

公开(公告)号：US20250013285A1

公开(公告)日：2025-01-09

申请号：US18349082

申请日：2023-07-07

Applicant: QUALCOMM Incorporated

Inventor： Alok KEDIYA ,  Manish PODDAR ,  Suresh VANKADARA ,  Mukund MITTAL ,  Gaurav GAGRANI

IPC: G06F1/3287 ,  G06F1/3237 ,  G06F1/324

Abstract: Aspects presented herein relate to methods and devices for data processing including an apparatus, e.g., a CPU. The apparatus may obtain an indication of a set of sensors that are connected to at least one clock source at a device. The apparatus may also detect whether each of the set of sensors is an active sensor or an inactive sensor. Further, the apparatus may select a clock configuration for a set of hardware components at the device based on the detection of whether each of the set of sensors is the active sensor or the inactive sensor, where the clock configuration is associated with the at least one clock source. The apparatus may also output an indication of the selected clock configuration for the set of hardware components at the device.