公开(公告)号：US11728003B2

公开(公告)日：2023-08-15

申请号：US17245981

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/18 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C7/1045 ,  G11C29/18 ,  G11C29/44 ,  G11C2029/1202

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US20210358559A1

公开(公告)日：2021-11-18

申请号：US17245981

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US09575884B2

公开(公告)日：2017-02-21

申请号：US13892433

申请日：2013-05-13

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Anand Srinivasan ,  Hyunsuk Shin ,  Steven Haehnichen

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.

Abstract translation: 方面包括用于增加闪存设备的闪存转换层（FTL）的性能的系统和方法。 存储在闪存设备上的FTL表的副本可以被复制到主机设备的存储器。 FTL表的副本可以由闪存设备直接访问，以在主机设备提供的逻辑地址之间转换用于从闪存设备的闪速存储器读取/写入操作的闪存以及闪存的相应物理地址 记忆。 闪存设备被授予对存储FTL表的副本的主机设备的存储器的一部分的直接存储器访问。 闪存设备总线将连接闪存设备的通信总线连接到主机设备的存储器。

公开(公告)号：US20140337560A1

公开(公告)日：2014-11-13

申请号：US13892433

申请日：2013-05-13

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Anand Srinivasan ,  Hyunsuk Shin ,  Steve Haehnichen

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.

Abstract translation: 方面包括用于增加闪存设备的闪存转换层（FTL）的性能的系统和方法。 存储在闪存设备上的FTL表的副本可以被复制到主机设备的存储器。 FTL表的副本可以由闪存设备直接访问，以在主机设备提供的逻辑地址之间转换用于从闪存设备的闪速存储器读取/写入操作的闪存以及闪存的相应物理地址 记忆。 闪存设备被授予对存储FTL表的副本的主机设备的存储器的一部分的直接存储器访问。 闪存设备总线将连接闪存设备的通信总线连接到主机设备的存储器。

公开(公告)号：US20250111885A1

公开(公告)日：2025-04-03

申请号：US18978617

申请日：2024-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US12230347B2

公开(公告)日：2025-02-18

申请号：US18322997

申请日：2023-05-24

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US20230298682A1

公开(公告)日：2023-09-21

申请号：US18322997

申请日：2023-05-24

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/18

CPC classification number: G11C29/42 ,  G11C29/44 ,  G11C7/1045 ,  G11C29/18 ,  G11C2029/1202

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.