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公开(公告)号:US20180165092A1
公开(公告)日:2018-06-14
申请号:US15379195
申请日:2016-12-14
Applicant: QUALCOMM Incorporated
Inventor: Yun Du , Liang Han , Lin Chen , Chihong Zhang , Hongjiang Shang , Jing Wu , Zilin Ying , Chun Yu , Guofang Jiao , Andrew Gruber , Eric Demers
Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.
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公开(公告)号:US10558460B2
公开(公告)日:2020-02-11
申请号:US15379195
申请日:2016-12-14
Applicant: QUALCOMM Incorporated
Inventor: Yun Du , Liang Han , Lin Chen , Chihong Zhang , Hongjiang Shang , Jing Wu , Zilin Ying , Chun Yu , Guofang Jiao , Andrew Gruber , Eric Demers
Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.
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