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1.发明申请公开(公告)号：US20160098276A1
公开(公告)日：2016-04-07
申请号：US14505854
申请日：2014-10-03
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Hongjiang Shang , Haikun Zhu
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F9/3012 , G06F9/30141 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/383 , G06F9/3832 , G06F9/3885 , G06F9/3887
Abstract: Techniques are described for determining whether execution of an instruction would require reading more values from a memory cell of a general purpose register (GPR) than a read port of the memory cell would allow. In such a case, the techniques may store, prior to execution of the instruction, one or more values from the memory cell in a separate conflict queue. During execution of the instruction to implement an operation defined by the instruction, one value that is an operand of the operation would be read from the memory cell and another value that is an operand of the operation other would be read from the conflict queue.
Abstract translation: 描述了用于确定指令的执行是否需要从通用目的寄存器（GPR）的存储器单元读取比存储器单元的读取端口将允许的更多值的技术。 在这种情况下，这些技术可以在执行指令之前在单独的冲突队列中存储来自存储器单元的一个或多个值。 在执行用于实现由指令定义的操作的指令期间，将从存储器单元读取作为操作的操作数的一个值，并且将从冲突队列读取作为其他操作的操作数的另一个值。
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公开(公告)号：US10558460B2
公开(公告)日：2020-02-11
申请号：US15379195
申请日：2016-12-14
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Liang Han , Lin Chen , Chihong Zhang , Hongjiang Shang , Jing Wu , Zilin Ying , Chun Yu , Guofang Jiao , Andrew Gruber , Eric Demers
Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.
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Patent Agency Ranking
公开(公告)号：US11829439B2
公开(公告)日：2023-11-28
申请号：US17137226
申请日：2020-12-29
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Gang Zhong , Fei Wei , Yibin Zhang , Jing Han , Hongjiang Shang , Elina Kamenetskaya , Minjie Huang , Alexei Vladimirovich Bourd , Chun Yu , Andrew Evan Gruber , Eric Demers
Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.
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公开(公告)号：US11094103B2
公开(公告)日：2021-08-17
申请号：US16364829
申请日：2019-03-26
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Andrew Evan Gruber , Chun Yu , Chihong Zhang , Hongjiang Shang , Zilin Ying , Fei Wei
Abstract: Example techniques are described for generating graphics content by obtaining texture operation instructions corresponding to a texture operation, in response to determining at least one of insufficient general purpose register space is available for the texture operation or insufficient wave slots are available for the texture operation, generating an indication that the texture operation corresponds to a deferred wave, executing the texture operation, sending, to a texture processor, initial texture sample instructions corresponding to the texture operation that was executed, and receiving texture mapped data corresponding to the initial texture sample instructions.
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公开(公告)号：US12229215B2
公开(公告)日：2025-02-18
申请号：US18487918
申请日：2023-10-16
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Gang Zhong , Fei Wei , Yibin Zhang , Jing Han , Hongjiang Shang , Elina Kamenetskaya , Minjie Huang , Alexei Vladimirovich Bourd , Chun Yu , Andrew Evan Gruber , Eric Demers
Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.
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公开(公告)号：US20180165092A1
公开(公告)日：2018-06-14
申请号：US15379195
申请日：2016-12-14
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Liang Han , Lin Chen , Chihong Zhang , Hongjiang Shang , Jing Wu , Zilin Ying , Chun Yu , Guofang Jiao , Andrew Gruber , Eric Demers
Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.
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公开(公告)号：US09632783B2
公开(公告)日：2017-04-25
申请号：US14505854
申请日：2014-10-03
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Hongjiang Shang , Haikun Zhu
CPC classification number: G06F9/30145 , G06F9/3012 , G06F9/30141 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/383 , G06F9/3832 , G06F9/3885 , G06F9/3887
Abstract: Techniques are described for determining whether execution of an instruction would require reading more values from a memory cell of a general purpose register (GPR) than a read port of the memory cell would allow. In such a case, the techniques may store, prior to execution of the instruction, one or more values from the memory cell in a separate conflict queue. During execution of the instruction to implement an operation defined by the instruction, one value that is an operand of the operation would be read from the memory cell and another value that is an operand of the operation other would be read from the conflict queue.
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