公开(公告)号：US11037651B2

公开(公告)日：2021-06-15

申请号：US16675676

申请日：2019-11-06

Applicant: QUALCOMM Incorporated

Inventor： Arvind Jain ,  Anju George ,  Swayam Pattnaik

IPC: G11C29/00 ,  G11C29/56 ,  G11C29/48 ,  G11C29/14 ,  G11C29/32

Abstract: Disclosed are methods and apparatus for securely accessing and testing a double data rate (DDR) memory device. The apparatus includes a first memory test access port (TAP) configured to enable or disable access to at least one double date rate (DDR) memory device, a second memory TAP configured to enable or disable access to at least one non-DDR memory device, and a test controller configured to test the at least one DDR memory device via the first memory TAP or test the at least one non-DDR memory device via the second memory TAP. In an aspect, at least one non-DDR memory device contains proprietary information. Accordingly, access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.