公开(公告)号：US20190096460A1

公开(公告)日：2019-03-28

申请号：US15842460

申请日：2017-12-14

Applicant: QUALCOMM Incorporated

Inventor： Bipin DUGGAL ,  Naishad PARIKH ,  Ritu CHABA

IPC: G11C8/18 ,  H03H11/26 ,  G11C7/10

Abstract: An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit coupled to one of the data input or the clock input. Additionally, the apparatus includes a controller coupled to the variable delay circuit. The controller is configured to dynamically control the delay of the variable delay circuit. The controller may adjust the delay of the variable delay circuit based on at least one of timing data for a memory subsystem design of the memory subsystem, timing data for the memory subsystem, a voltage applied to the memory subsystem, or a temperature of the memory subsystem.