公开(公告)号：US20150357013A1

公开(公告)日：2015-12-10

申请号：US14298819

申请日：2014-06-06

Applicant: QUALCOMM Incorporated

Inventor： Alex Dongkyu PARK ,  Venkatasubramanian NARAYANAN ,  Ritu CHABA ,  Derek Xiaoxiang YANG ,  Arun Babu PALLERLA

IPC: G11C7/12 ,  G11C11/417

CPC classification number: G11C7/12 ,  G11C7/227 ,  G11C11/417 ,  G11C11/419

Abstract: A memory and a method for operating the memory are provided. The memory includes a bitline and at least one memory cell coupled to the bitline. A bitline precharge circuit is configured to precharge the bitline for a memory access and to deactivate to float the bitline in a standby state. A reference circuit is configured to charge a load circuit to a voltage in the standby state. In one example, the load circuit includes a dummy bitline having a substantially same or greater electrical characteristic of the bitline. The reference circuit includes a dummy bitline precharge circuit configured to charge the dummy bitline to the voltage in the standby state.

Abstract translation: 提供了用于操作存储器的存储器和方法。 存储器包括位线和耦合到位线的至少一个存储器单元。 位线预充电电路被配置为为存储器访问预充电位线，并且停用以将位线浮置在待机状态。 参考电路被配置为将负载电路充电到待机状态的电压。 在一个示例中，负载电路包括具有基本相同或更大的位线电特性的虚拟位线。 参考电路包括虚拟位线预充电电路，其被配置为将虚拟位线充电至待机状态的电压。

公开(公告)号：US20210134358A1

公开(公告)日：2021-05-06

申请号：US17144077

申请日：2021-01-07

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Keejong KIM ,  Chulmin JUNG ,  Ritu CHABA

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418

Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

公开(公告)号：US20150063046A1

公开(公告)日：2015-03-05

申请号：US14018404

申请日：2013-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： Rakesh Kumar SINHA ,  Chirag GULATI ,  Ritu CHABA ,  Sei Seung YOON

IPC: G11C7/06 ,  G11C7/04

CPC classification number: G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/227

Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.

Abstract translation: 公开了具有多字线设计的存储器的各种装置和方法。 存储器定时电路可以包括包括第一部分和第二部分的虚拟字线，并且还包括集中在伪字线的第二部分中的电容负载，连接到虚拟字线的第一部分的第一晶体管和 被配置为对所述虚拟字线充电;以及第二晶体管，连接到所述虚拟字线的第二部分，并且被配置为对所述虚拟字线进行放电。 一种方法可以包括使用第一晶体管对虚拟字线进行充电，以及使用第二晶体管对该虚拟字线进行放电，其中，所述虚拟字线包括第一部分和第二部分，并且还包括集中在所述第二部分中的电容负载 的虚拟字线。

公开(公告)号：US20190096460A1

公开(公告)日：2019-03-28

申请号：US15842460

申请日：2017-12-14

Applicant: QUALCOMM Incorporated

Inventor： Bipin DUGGAL ,  Naishad PARIKH ,  Ritu CHABA

IPC: G11C8/18 ,  H03H11/26 ,  G11C7/10

Abstract: An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit coupled to one of the data input or the clock input. Additionally, the apparatus includes a controller coupled to the variable delay circuit. The controller is configured to dynamically control the delay of the variable delay circuit. The controller may adjust the delay of the variable delay circuit based on at least one of timing data for a memory subsystem design of the memory subsystem, timing data for the memory subsystem, a voltage applied to the memory subsystem, or a temperature of the memory subsystem.

公开(公告)号：US20150058686A1

公开(公告)日：2015-02-26

申请号：US13975277

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Chirag GULATI ,  Ritu CHABA ,  Lakshmikantha HOLLA VAKWADI

IPC: G01R31/3185

CPC classification number: G01R31/318541 ,  G01R31/318597 ,  G11C29/32 ,  G11C29/36 ,  G11C2029/3202 ,  G11C2029/3602

Abstract: A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.

Abstract translation: 提供了在功能模式和ATPG扫描模式下操作装置的方法以及用于功能模式和ATPG扫描模式的装置。 该装置包括一组锁存器，其包括第一锁存器和第二锁存器。 第一个锁存器作为主锁存器操作，第二个锁存器在功能模式下作为主锁存器运行。 第一个锁存器作为触发器的主锁存器操作，第二个锁存器在ATPG扫描模式下作为触发器的从锁存器操作。 在一种配置中，该装置包括至少包括第一和第二锁存器的多个锁存器，每个锁存器的输出耦合到数字电路，该装置包括多个功能输入，并且每个功能输入是 输入到数字电路。

公开(公告)号：US20150085568A1

公开(公告)日：2015-03-26

申请号：US14038434

申请日：2013-09-26

Applicant: QUALCOMM Incorporated

Inventor： Chirag GULATI ,  Rakesh SINHA ,  Ritu CHABA ,  Sei Seung YOON

IPC: G11C11/419 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C8/14 ,  H01L27/1104 ,  H01L27/1116

Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Abstract translation: 集成电路包括一个或多个位单元，耦合到所述一个或多个位单元的字线以及与所述字线布置以在其间具有电容的虚拟字线。 该电容提供了字线的升压或降压以辅助读和写操作。

公开(公告)号：US20150067290A1

公开(公告)日：2015-03-05

申请号：US14018399

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Ritu CHABA ,  Balachander GANESAN ,  ChangHo JUNG ,  Sei Seung YOON

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G06F2212/1028

Abstract: Disclosed are various apparatuses and methods for memory access time tracking in dual-rail systems. An apparatus may include a memory coupled to a first voltage rail and having a data output, a data circuit coupled to a second voltage rail and configured to receive the data output from the memory, and a timing circuit configured to adjust an access time of the memory based on a second voltage rail level. A method may include determining a voltage rail level of a data circuit, adjusting the access time of the memory based on the voltage rail level of the data circuit, outputting data from the memory, and receiving the output data by the data circuit.

Abstract translation: 公开了用于双轨系统中的存储器访问时间跟踪的各种装置和方法。 设备可以包括耦合到第一电压轨并具有数据输出的存储器，耦合到第二电压轨并被配置为接收从存储器输出的数据的数据电路，以及定时电路，被配置为调整存储器的访问时间 基于第二电压轨级的存储器。 一种方法可以包括确定数据电路的电压轨级，基于数据电路的电压轨电平调整存储器的访问时间，从存储器输出数据，以及由数据电路接收输出数据。