公开(公告)号：US11114175B1

公开(公告)日：2021-09-07

申请号：US16986541

申请日：2020-08-06

Applicant: QUALCOMM Incorporated

Inventor： Paramjeet Singh ,  Bipin Duggal

IPC: G11C17/12

Abstract: A Read Only Memory (ROM) cell array includes: a first transistor coupled to a first word line; a second transistor coupled to a second word line; and a third transistor disposed between the first transistor and the second transistor, the third transistor having a first gate terminal permanently coupled to a power rail.

公开(公告)号：US20190041440A1

公开(公告)日：2019-02-07

申请号：US15667116

申请日：2017-08-02

Applicant: QUALCOMM Incorporated

Inventor： Bipin Duggal ,  Rahul Gulati ,  Sina Dena

IPC: G01R23/02 ,  G01R35/00

Abstract: In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

公开(公告)号：US10514401B2

公开(公告)日：2019-12-24

申请号：US15667116

申请日：2017-08-02

Applicant: QUALCOMM Incorporated

Inventor： Bipin Duggal ,  Rahul Gulati ,  Sina Dena

IPC: G01R23/02 ,  G01R31/317 ,  G01R23/10 ,  G01R23/15 ,  G01R35/00 ,  G01R23/14 ,  G01R23/00

Abstract: In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

公开(公告)号：US20190107569A1

公开(公告)日：2019-04-11

申请号：US15730486

申请日：2017-10-11

Applicant: QUALCOMM Incorporated

Inventor： David Kidd ,  Ardavan Moassessi ,  Angelo Pinto ,  Albert Kumar ,  Yi Lou ,  Bipin Duggal ,  Amar Gulhane ,  Michael Bourland ,  Mustafa Badaroglu ,  Paul Penzes

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/36 ,  H01L21/66

Abstract: Aspects of the disclosure includes a transistor-under-test (TUT) to charge/discharge a capacitor; changing an oscillation state when a capacitor voltage crosses a threshold and turning OFF the TUT; discharging the capacitor using the TUT; commencing precharging the capacitor after detecting the capacitor reaches a transition voltage; commencing discharging the capacitor after a precharger time delay; sustaining a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF/ON the TUT; and generating a digital representation of a TUT current associated with a relaxation oscillator period of the relaxation oscillator waveform. For example, a measurement tile includes a pulse generator to sustain the relaxation oscillator waveform with the relaxation oscillator period associated with an inverse TUT current; and a precharger charging a capacitor and the TUT charging/discharging the capacitor, wherein the relaxation oscillator waveform is based on turning OFF/ON the TUT in accordance with discharging and charging the capacitor.