公开(公告)号：US12248365B2

公开(公告)日：2025-03-11

申请号：US18183833

申请日：2023-03-14

Applicant: QUALCOMM Incorporated

Inventor： Umesh Srikantiah ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Boris Alpin ,  Francesco Gatta

IPC: G06F11/07 ,  G06F13/42

Abstract: A receiving circuit has a clock generator circuit, a synchronization circuit and a controller. The clock generator circuit is configured to generate a base clock signal with a base frequency. The synchronization circuit is configured to synchronize edges in the base clock signal with edges in a Manchester-encoded data signal received over a serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition that indicates a first type of transaction during which the Manchester-encoded data signal is received over the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse when signaling consistent with the first type of sequence start condition has not been received before the first timer expires.