公开(公告)号：US09024658B2

公开(公告)日：2015-05-05

申请号：US13905060

申请日：2013-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jay Madhukar Shah ,  Chethan Swamynathan ,  Animesh Datta

IPC: H03K19/02 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318541

Abstract: Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

Abstract translation: 本文描述了用于减少可扫描的翻转托盘中的扫描开销的技术。 在一个实施例中，用于翻转托盘的扫描电路包括三态电路，其被配置为反转输入数据信号，并将反相数据信号以正常模式输出到翻转托盘的触发器的输入，并阻塞 来自触发器的输入的扫描模式的数据信号。 扫描电路还包括一个通道门，其被配置为在扫描模式下将扫描信号传递到触发器的输入，并且在正常模式下阻止来自触发器的输入的扫描信号。

公开(公告)号：US10141297B1

公开(公告)日：2018-11-27

申请号：US15830173

申请日：2017-12-04

Applicant: QUALCOMM Incorporated

Inventor： Palkesh Jain ,  Mehdi Saeidi ,  Jon James Anderson ,  Chethan Swamynathan ,  Richard Wunderlich

IPC: H01L27/02 ,  G06F17/50

Abstract: An integrated device that includes a substrate, a device level layer formed over the substrate, and interconnect portion over the device level layer. The device level layer includes a plurality of first device level cells, each first device level cell comprising a first configuration. The device level layer includes a plurality of second device level cells. At least one second device level cell includes a second configuration that is different than the first configuration. The plurality of second device level cells is located over at least one region of the integrated device comprising at least one hotspot.

公开(公告)号：US20140359385A1

公开(公告)日：2014-12-04

申请号：US13905060

申请日：2013-05-29

Applicant: QUALCOMM INCORPORATED

Inventor： Jay Madhukar Shah ,  Chethan Swamynathan ,  Animesh Datta

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318541

Abstract: Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

Abstract translation: 本文描述了用于减少可扫描的翻转托盘中的扫描开销的技术。 在一个实施例中，用于翻转托盘的扫描电路包括三态电路，其被配置为反转输入数据信号，并将反相数据信号以正常模式输出到翻转托盘的触发器的输入，并阻塞 来自触发器的输入的扫描模式的数据信号。 扫描电路还包括一个通道门，其被配置为在扫描模式下将扫描信号传递到触发器的输入，并且在正常模式下阻止来自触发器的输入的扫描信号。