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    Stacked common gate finFET devices for area optimization
    1.
    发明授权
    Stacked common gate finFET devices for area optimization 有权
    用于区域优化的堆叠公共栅极finFET器件

    公开(公告)号：US09397101B2

    公开(公告)日：2016-07-19

    申请号：US14458228

    申请日：2014-08-12

    Applicant: QUALCOMM Incorporated

    Inventor： HariKrishna Chintarlapalli Reddy ,  Jay Madhukar Shah ,  Ananth Haliyur Gopalakrishna

    IPC: H01L27/118 ,  H01L27/092 ,  H01L27/088 ,  H01L27/02

    CPC classification number: H01L27/0924 ,  H01L27/0207 ,  H01L27/0886

    Abstract: A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.

    Abstract translation: MOS器件包括具有第一晶体管源极，漏极，栅极和鳍片组的第一FinFET，并且包括具有第二晶体管源极，漏极，栅极和鳍片组的第二FinFET。 MOS器件进一步包括栅极互连线性地延伸以形成并将第一和第二晶体管栅极连接在一起。 所述MOS器件还包括在所述栅极互连的第一侧上的第一互连，所述第一互连将所述第一晶体管漏极处的所述第一晶体管鳍片集合在所述第二晶体管源处的所述第二晶体管鳍片组， 在第一晶体管源处将第一晶体管鳍片集合在一起的栅极互连以及栅极互连的第二侧上的第三互连，其将第二晶体管漏极的第二晶体管鳍片组连接在一起。

    FLIP-FLOP WITH REDUCED RETENTION VOLTAGE
    2.
    发明申请
    FLIP-FLOP WITH REDUCED RETENTION VOLTAGE 有权
    FLIP-FLOP具有降低的保持电压

    公开(公告)号：US20140306735A1

    公开(公告)日：2014-10-16

    申请号：US13862015

    申请日：2013-04-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Jay Madhukar Shah ,  Martin Saint-Laurent ,  Peeyush Kumar Parkar ,  Sachin Bapat ,  Ramaprasath Vilangudipitchai ,  Mohamed Hassan Abu-Rahma ,  Prayag Bhanubhai Patel

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

    Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

    Abstract translation: 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应控制信号来控制从机级。

    CIRCUIT AND LAYOUT TECHNIQUES FOR FLOP TRAY AREA AND POWER OTIMIZATION
    3.
    发明申请
    CIRCUIT AND LAYOUT TECHNIQUES FOR FLOP TRAY AREA AND POWER OTIMIZATION 有权
    流动盘区和电力监控的电路和布局技术

    公开(公告)号：US20140359385A1

    公开(公告)日：2014-12-04

    申请号：US13905060

    申请日：2013-05-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： Jay Madhukar Shah ,  Chethan Swamynathan ,  Animesh Datta

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/318541

    Abstract: Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

    Abstract translation: 本文描述了用于减少可扫描的翻转托盘中的扫描开销的技术。 在一个实施例中，用于翻转托盘的扫描电路包括三态电路，其被配置为反转输入数据信号，并将反相数据信号以正常模式输出到翻转托盘的触发器的输入，并阻塞 来自触发器的输入的扫描模式的数据信号。 扫描电路还包括一个通道门，其被配置为在扫描模式下将扫描信号传递到触发器的输入，并且在正常模式下阻止来自触发器的输入的扫描信号。

    Adaptive standard cell architecture and layout techniques for low area digital SoC
    5.
    发明授权
    Adaptive standard cell architecture and layout techniques for low area digital SoC 有权
    低面积数字SoC的自适应标准单元架构和布局技术

    公开(公告)号：US09070552B1

    公开(公告)日：2015-06-30

    申请号：US14267888

    申请日：2014-05-01

    Applicant: QUALCOMM Incorporated

    Inventor： Jay Madhukar Shah ,  Kamesh Medisetti ,  Vijayalakshmi Ranganna ,  Animesh Datta

    IPC: H01L23/52 ,  H01L27/02 ,  H01L23/528

    CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L27/11807 ,  H01L2027/11881 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A standard cell CMOS device includes a first power rail extending across the standard cell. The first power rail is connected to one of a first voltage or a second voltage less than the first voltage. The device further includes a second power rail extending across the standard cell. The second power rail is connected to an other one of the first voltage or the second voltage. The second power rail includes a metal x layer interconnect and a set of metal x−1 layer interconnects connected to the metal x layer interconnect. The device further includes a set of CMOS transistor devices between the first and second power rails and powered by the first and second power rails. The device further includes an x−1 layer interconnect extending under and orthogonal to the second power rail. The x−1 layer interconnect is coupled to the set of CMOS transistor devices.

    Abstract translation: 标准单元CMOS器件包括跨标准单元延伸的第一电源轨。 第一电源轨连接到小于第一电压的第一电压或第二电压之一。 该装置还包括延伸穿过标准单元的第二电力轨道。 第二电源轨连接到第一电压或第二电压中的另一个。 第二电源轨包括金属x层互连和连接到金属x层互连的一组金属x-1层互连。 该器件还包括在第一和第二电源轨之间的一组CMOS晶体管器件，并由第一和第二电源轨提供动力。 该装置还包括延伸在第二电力轨下并正交于第二电力轨道的x-1层互连。 x-1层互连耦合到该组CMOS晶体管器件。

    Circuit and layout techniques for flop tray area and power otimization
    6.
    发明授权
    Circuit and layout techniques for flop tray area and power otimization 有权
    翻牌托盘面积和功耗的电路和布局技术

    公开(公告)号：US09024658B2

    公开(公告)日：2015-05-05

    申请号：US13905060

    申请日：2013-05-29

    Applicant: QUALCOMM Incorporated

    Inventor： Jay Madhukar Shah ,  Chethan Swamynathan ,  Animesh Datta

    IPC: H03K19/02 ,  G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/318541

    Abstract: Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

    Abstract translation: 本文描述了用于减少可扫描的翻转托盘中的扫描开销的技术。 在一个实施例中，用于翻转托盘的扫描电路包括三态电路，其被配置为反转输入数据信号，并将反相数据信号以正常模式输出到翻转托盘的触发器的输入，并阻塞 来自触发器的输入的扫描模式的数据信号。 扫描电路还包括一个通道门，其被配置为在扫描模式下将扫描信号传递到触发器的输入，并且在正常模式下阻止来自触发器的输入的扫描信号。

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