公开(公告)号：US10140224B2

公开(公告)日：2018-11-27

申请号：US15461184

申请日：2017-03-16

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Sharad Kumar Gupta ,  Dharaneedharan Shanmugasundaram

IPC: G11C11/00 ,  G06F13/16 ,  G11C7/10 ,  G11C11/418 ,  G11C11/419 ,  G11C7/02 ,  G11C7/12

Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.