公开(公告)号：US20230096035A1

公开(公告)日：2023-03-30

申请号：US17449630

申请日：2021-09-30

Applicant: QUALCOMM Incorporated

Inventor： Sushil CHAUHAN ,  Mahesh AIA ,  Dileep MARCHYA

IPC: G09G5/377 ,  G06T1/20

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for parallelization of GPU composition with DPU topology selection. A processor may receive an indication of a plurality of application layers for composition at a first processor (e.g., a DPU) and a second processor (e.g., a GPU). The processor may select one or more first application layers of the plurality of application layers for attempted composition at the first processor and one or more second application layers of the plurality of application layers for composition at the second processor. The processor may transmit each of the one or more first application layers to the first processor for composition and each of the one or more second application layers to the second processor for composition.

公开(公告)号：US20200184928A1

公开(公告)日：2020-06-11

申请号：US16215170

申请日：2018-12-10

Applicant: QUALCOMM Incorporated

Inventor： Dileep MARCHYA ,  Balamukund SRIPADA ,  Srinivas PULLAKAVI

IPC: G09G5/12

Abstract: Certain aspects of the present disclosure provide a method for driving a plurality of display panels including a first display panel and a second display panel. The method includes receiving a first synchronization signal from the first display panel. The method further includes receiving a second synchronization signal from the second display panel. The method further includes determining a phase difference between the first synchronization signal and the second synchronization signal. The method further includes computing at least one phase shift offset based on the determined phase difference, the at least one phase shift offset being configured to reduce the phase difference between the first synchronization signal and the second synchronization signal. The method further includes providing a first phase shift offset of the at least one phase shift offset to the first display panel. The method further includes providing a unified synchronization signal to a display processor.

公开(公告)号：US20240290295A1

公开(公告)日：2024-08-29

申请号：US18176355

申请日：2023-02-28

Applicant: QUALCOMM Incorporated

Inventor： Padmanabhan KOMANDURU V ,  Srinivas PULLAKAVI ,  Dileep MARCHYA

IPC: G09G5/00 ,  G06T1/20

CPC classification number: G09G5/003 ,  G06T1/20 ,  G09G2320/0266 ,  G09G2340/0435

Abstract: Aspects of the disclosure are directed to implementing adaptive variable refresh (AVR) wherein a graphics processing unit (GPU) is configured to generate a display content; a display processing unit (DPU) coupled to the graphics processing unit (GPU), wherein the DPU is configured to provide an adaptive variable refresh (AVR) feature; and a display panel coupled to the DPU, wherein the display panel is configured to display the display content.

公开(公告)号：US20200225728A1

公开(公告)日：2020-07-16

申请号：US16248008

申请日：2019-01-15

Applicant: QUALCOMM Incorporated

Inventor： Dileep MARCHYA ,  Samson KIM

IPC: G06F1/3234 ,  G06F3/0481 ,  H04N19/423

Abstract: A method, an apparatus, and a computer-readable medium for displaying a blinking cursor are provided in a power-efficient manner. Various hardware and protocol command enhancements are provided allowing a visible cursor frame region and an invisible cursor frame region are sequentially displayed creating the blinking cursor effect. Further support is provided for compressed frames, for example, frames compressed with the VESA Display Stream Compression (DSC) standard.

公开(公告)号：US20190156785A1

公开(公告)日：2019-05-23

申请号：US15818650

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Dileep MARCHYA ,  Balamukund SRIPADA ,  Srinivas PULLAKAVI

IPC: G09G5/10

Abstract: A method and system for displaying image data on a video-mode display panel is provided. Instead of continuously refreshing the entire display panel, the display panel may be divided into a first frame region and a second frame region. Each frame region may be associated with its own refresh rate. A higher refresh rate can be provided to content such as video playback and scrolling where a higher refresh rate is required for improved user experience and reduce visual artifacts. A lower refresh rate can be provided to other content, thus saving power where higher refresh rate is not required.

公开(公告)号：US20250037683A1

公开(公告)日：2025-01-30

申请号：US18709469

申请日：2023-01-05

Applicant: QUALCOMM Incorporated

Inventor： Padmanabhan KOMANDURU V ,  Dileep MARCHYA ,  Srinivas PULLAKAVI

IPC: G09G5/395 ,  G09G5/12 ,  G09G5/18

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for DPU driven adaptive synchronization for command mode displays. A display processor may obtain one or more frame content buffers for a frame composition cycle. The display processor may obtain a fence for the one or more frame content buffers. The display processor may receive a signal for the fence for the one or more frame content buffers. The display processor may compose a first frame associated with the one or more frame content buffers for the frame composition cycle. The display processor may transfer, to a display memory of a display, data for the first frame associated with a first synchronization signal. The data for the first frame may be transferred at a default transfer rate or a boosted transfer rate.

公开(公告)号：US20220343459A1

公开(公告)日：2022-10-27

申请号：US17753681

申请日：2020-10-14

Applicant: QUALCOMM Incorporated

Inventor： Nan ZHANG ,  Yongjun XU ,  Dileep MARCHYA

IPC: G06T3/40 ,  G06T1/20

Abstract: The present disclosure relates to methods and apparatus for display processing. For example, disclosed techniques facilitate regional processing of images for under-display device displays. Aspects of the present disclosure can identify a subsection of a set of frame layers, the identified subsection corresponding to a lower pixel density region, relative to at least one other region, of a display. Aspects of the present disclosure can also blend first pixel data for each frame layer corresponding to the identified subsection to generate second pixel data. Further, aspects of the present disclosure can populate a buffer layer based on the second pixel data. Additionally, aspects of the present disclosure can blend pixel data from the set of frame layers and the buffer layers to generate a blended image. Aspects of the present disclosure can also transmit the blended image for presentment via the display.

公开(公告)号：US20200035192A1

公开(公告)日：2020-01-30

申请号：US16048098

申请日：2018-07-27

Applicant: QUALCOMM Incorporated

Inventor： Dileep MARCHYA ,  Balamukund SRIPADA

IPC: G09G5/00

Abstract: A method, an apparatus, and a computer-readable medium for wireless communication are provided. In one aspect, an example method may include causing a first region of a display to be refreshed without using a memory of the display, and causing a second region of the display to be refreshed using the memory of the display.

公开(公告)号：US20240169953A1

公开(公告)日：2024-05-23

申请号：US18057750

申请日：2022-11-21

Applicant: QUALCOMM Incorporated

Inventor： Dileep MARCHYA ,  Padmanabhan KOMANDURU V ,  Srinivas PULLAKAVI

IPC: G09G5/00 ,  G09G5/393 ,  G09G5/395

CPC classification number: G09G5/006 ,  G09G5/393 ,  G09G5/395 ,  G09G2310/04 ,  G09G2330/021 ,  G09G2350/00 ,  G09G2360/121 ,  G09G2360/18 ,  G09G2370/10

Abstract: Aspects presented herein relate to methods and devices for display processing including an apparatus, e.g., a CPU. The apparatus may perform a partial frame update for a first frame at a first update time, where the partial frame update corresponds to an update of less than all content in the first frame, where the partial frame update for the first frame is associated with a panel ROI of the first frame. The apparatus may also calculate a margin time period between the first update time and a subsequent Vsync time. Further, the apparatus may transmit, based on the margin time period, a first indication of a subsequent frame transfer interrupt time. The apparatus may also transmit, to a DPU, a second indication to transfer the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting at the subsequent frame transfer interrupt time.

公开(公告)号：US20220013087A1

公开(公告)日：2022-01-13

申请号：US16924052

申请日：2020-07-08

Applicant: QUALCOMM Incorporated

Inventor： Dileep MARCHYA ,  Srinivas PULLAKAVI ,  Padmanabhan KOMANDURU V

IPC: G09G5/36 ,  G09G5/377 ,  G09G5/395

Abstract: The present disclosure relates to methods and apparatus for display processing. The apparatus can receive a first frame at a frame ready time associated with a current vertical synchronization (Vsync) time period including a first Vsync time and a second Vsync time, the frame ready time may be between the first Vsync time and the second Vsync time, the current Vsync time period may be distinct from one or more application Vsync time periods. The apparatus can also determine one of the one or more application Vsync time periods to align with the current Vsync time period based on the frame ready time. Moreover, the apparatus can adjust an alignment of the current Vsync time period to align with the one of the one or more application Vsync time periods. The apparatus can also adjust the second Vsync time to align the current Vsync time period.