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    Providing input/output virtualization (IOV) by mapping transfer requests to shared transfer requests lists by IOV host controllers
    2.
    发明授权
    Providing input/output virtualization (IOV) by mapping transfer requests to shared transfer requests lists by IOV host controllers 有权

    公开(公告)号：US09542340B2

    公开(公告)日：2017-01-10

    申请号：US14728343

    申请日：2015-06-02

    Applicant: QUALCOMM Incorporated

    Inventor： Assaf Shacham ,  Dolev Raviv ,  David Teb

    IPC: G06F12/00 ,  G06F13/16 ,  G06F3/06

    Abstract: An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.

    Ascertaining command completion in flash memories
    3.
    发明授权
    Ascertaining command completion in flash memories 有权
    确定闪存中的命令完成

    公开(公告)号：US09348537B2

    公开(公告)日：2016-05-24

    申请号：US14467404

    申请日：2014-08-25

    Applicant: QUALCOMM Incorporated

    Inventor： Dolev Raviv ,  Tatyana Brokhman ,  Maya Haim ,  Assaf Shacham

    IPC: G06F3/06 ,  G06F13/38

    CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G06F13/385 ,  G06F2206/1014

    Abstract: Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host—a hardware component—may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared.

    Abstract translation: 公开闪存中的确定命令完成。 示例性方面包括消除软件锁定和未完成的请求变量并用传送请求完成寄存器替换它们。 转移请求完成寄存器可以映射到通用闪存存储（UFS）传输协议（UTP）传输请求列表（UTRL）槽。 主机的控制器 - 硬件组件 - 可以在转移请求完成时将门铃寄存器清零的同时设置在传送请求完成寄存器中的位。 读取该位后，转移请求完成寄存器中的位将被清零。

    INPUT/OUTPUT VIRTUALIZATION (IOV) HOST CONTROLLER (HC) (IOV-HC) OF A FLASH-MEMORY-BASED STORAGE DEVICE
    5.
    发明申请
    INPUT/OUTPUT VIRTUALIZATION (IOV) HOST CONTROLLER (HC) (IOV-HC) OF A FLASH-MEMORY-BASED STORAGE DEVICE 有权
    基于闪存存储器的存储设备的输入/输出虚拟化（IOV）主机控制器（HC）（IOV-HC）

    公开(公告)号：US20150347016A1

    公开(公告)日：2015-12-03

    申请号：US14728343

    申请日：2015-06-02

    Applicant: QUALCOMM Incorporated

    Inventor： Assaf Shacham ,  Dolev Raviv ,  David Teb

    IPC: G06F3/06

    CPC classification number: G06F13/16 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0664 ,  G06F3/0688 ,  G11C7/00

    Abstract: An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.

    Abstract translation: 公开了一种基于闪存存储器的存储设备的输入/输出虚拟化（IOY）主机控制器（HC）（IOV-HC）。 在一个方面，IOV-HC通过相应的客户端寄存器接口（CRI）耦合到输入/输出（I / O）客户端，并且还耦合到基于闪存存储器的存储设备。 IOV-HC包括指示被分配为每个CRI的基准时隙的共享TRL的时隙的传送请求列表（TRL）时隙偏移量寄存器。 IOV-HC还包括TRL时隙计数寄存器，其指示共享TRL的多少时隙被分配给每个CRI。 当从CRI接收到指向基于闪速存储器的存储设备的传送请求（TR）时，IOV-HC被配置为基于TRL时隙偏移寄存器和TRL将TR映射到共享TRL的时隙 对应于CRI的多个TRL时隙计数寄存器的时隙计数寄存器。

    ASCERTAINING COMMAND COMPLETION IN FLASH MEMORIES
    6.
    发明申请
    ASCERTAINING COMMAND COMPLETION IN FLASH MEMORIES 有权
    闪存记忆中的命令完成

    公开(公告)号：US20150074338A1

    公开(公告)日：2015-03-12

    申请号：US14467404

    申请日：2014-08-25

    Applicant: QUALCOMM Incorporated

    Inventor： Dolev Raviv ,  Tatyana Brokhman ,  Maya Haim ,  Assaf Shacham

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G06F13/385 ,  G06F2206/1014

    Abstract: Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host—a hardware component—may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared.

    Abstract translation: 公开闪存中的确定命令完成。 示例性方面包括消除软件锁定和未完成的请求变量并用传送请求完成寄存器替换它们。 转移请求完成寄存器可以映射到通用闪存存储（UFS）传输协议（UTP）传输请求列表（UTRL）槽。 主机的控制器 - 硬件组件 - 可以在转移请求完成时将门铃寄存器清零的同时设置在传送请求完成寄存器中的位。 读取该位后，转移请求完成寄存器中的位将被清零。

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