Configuring optimal bus turnaround cycles for master-driven serial buses

    公开(公告)号:US10445270B2

    公开(公告)日:2019-10-15

    申请号:US15994754

    申请日:2018-05-31

    Abstract: Systems, methods, and apparatus for optimizing bus turnaround in a master-driven serial bus are described. A method performed at a master device coupled to a serial bus includes configuring slave devices coupled to the serial bus with respective delay values that define bus turnaround wait periods, transmitting a first read command directed to a first slave device, receiving data after a first wait period initiated after the first read command has been sent, the first wait period being defined by a delay value configured in the first slave device, transmitting a second read command directed to a second slave device, and receiving data after a second wait period initiated after the second read command has been sent, the second wait period being defined by a delay value configured in the second slave device. The first wait period and the second wait period may have different durations.

    Super-speed UART with pre-frame bit-rate and independent variable upstream and downstream rates

    公开(公告)号:US10447464B2

    公开(公告)日:2019-10-15

    申请号:US16173949

    申请日:2018-10-29

    Abstract: Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a receiving device includes detecting a first transition in a signal received from a receive line of a UART after the receive line has been idle or following transmission of a stop bit on the receive line, detecting a second transition in the signal, synchronizing a sampling clock to the second transition, where clock cycles of the sampling clock are double the duration between the first transition and the second transition, and using the sampling clock to capture a byte of data from the receive line. One clock cycle of the sampling clock may be consumed while receiving each bit of data.

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