公开(公告)号：US20230005556A1

公开(公告)日：2023-01-05

申请号：US17364738

申请日：2021-06-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul SAHU ,  Sharad Kumar GUPTA ,  Jung Pill KIM ,  Chulmin JUNG ,  Jais ABRAHAM

IPC: G11C29/10 ,  G11C7/06 ,  G11C7/10

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

公开(公告)号：US20200233031A1

公开(公告)日：2020-07-23

申请号：US16255214

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jais ABRAHAM ,  Punit KISHORE

IPC: G01R31/317 ,  G01R31/3185

Abstract: Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.

公开(公告)号：US20240221853A1

公开(公告)日：2024-07-04

申请号：US18605685

申请日：2024-03-14

Applicant: QUALCOMM Incorporated

Inventor： Rahul SAHU ,  Sharad Kumar GUPTA ,  Jung Pill KIM ,  Chulmin JUNG ,  Jais ABRAHAM

IPC: G11C29/10 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C29/10 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1096

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.