公开(公告)号：US20240372535A1

公开(公告)日：2024-11-07

申请号：US18312317

申请日：2023-05-04

Applicant: QUALCOMM Incorporated

Inventor： Andrew WEIL ,  Jaswinder SINGH ,  Sameer WADHWA ,  Dongwon SEO

IPC: H03K3/017 ,  H03K5/156

Abstract: A duty cycle correction circuit includes four pairs of serially coupled transistors. A first two of the serial pairs of transistors couple between an internal node for complement output clock signal and ground. A second two of the serial pairs of transistors couple between the internal node and a power supply node for a power supply voltage. Each serial pair is controlled by a corresponding pair of quadrature clock signals in which one of the quadrature clock signal is delayed with respect to the other quadrature clock signal be one quarter of a clock period. The first two serial pairs of transistors thus combine to discharge the internal node for one-half clock period whereas the second two serial pairs of transistors combine to charge the internal node for one-half clock period so that the complement output clock signal has a 50% duty cycle.