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    LOW HEADROOM CASCODE BIAS CIRCUIT FOR CASCODE CURRENT MIRRORS
    1.
    发明公开
    LOW HEADROOM CASCODE BIAS CIRCUIT FOR CASCODE CURRENT MIRRORS 审中-公开

    公开(公告)号：US20240152170A1

    公开(公告)日：2024-05-09

    申请号：US17982420

    申请日：2022-11-07

    Applicant: QUALCOMM Incorporated

    Inventor： Andrew WEIL

    IPC: G05F3/26

    CPC classification number: G05F3/262

    Abstract: A cascode bias circuit biases a gate of a cascode transistor in a cascode current mirror. The cascode bias circuit includes a first transistor configured to conduct a first current and includes a second transistor configured to conduct a second current. The first and second transistors couple to a third transistor configured to conduct a sum of the first current and the second current. A gate of the first transistor couples to a gate of the cascode transistor to bias the cascode transistor.

    DIGITAL-TO-ANALOG CONVERTER (DAC) WITH DYNAMIC STACKED CASCODE SWITCHES
    2.
    发明申请
    DIGITAL-TO-ANALOG CONVERTER (DAC) WITH DYNAMIC STACKED CASCODE SWITCHES 有权

    公开(公告)号：US20240429937A1

    公开(公告)日：2024-12-26

    申请号：US18338708

    申请日：2023-06-21

    Applicant: QUALCOMM Incorporated

    Inventor： Xiahan ZHOU ,  Haibo FEI ,  Nitz SAPUTRA ,  Andrew WEIL

    IPC: H03M1/74

    Abstract: Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.

    LOAD MATCHING FOR A CURRENT-STEERING DIGITAL-TO-ANALOG CONVERTER
    4.
    发明公开
    LOAD MATCHING FOR A CURRENT-STEERING DIGITAL-TO-ANALOG CONVERTER 审中-公开

    公开(公告)号：US20240322838A1

    公开(公告)日：2024-09-26

    申请号：US18189350

    申请日：2023-03-24

    Applicant: QUALCOMM Incorporated

    Inventor： Andrew WEIL

    IPC: H03M1/74 ,  H03M1/06 ,  H03M1/68

    CPC classification number: H03M1/742 ,  H03M1/068 ,  H03M1/687

    Abstract: Certain aspects of the present disclosure are directed towards a digital-to-analog converter (DAC) system. The DAC system generally includes a first driver and a plurality of current-steering cells. A first current-steering cell of the plurality of current-steering cells includes: a first current source coupled to a first current-steering transistor and a second current-steering transistor, wherein a gate of the first current-steering transistor and a gate of the second current-steering transistor are coupled to a first output and a second output of the first driver, respectively; a first transistor having a source coupled to a current source path and a drain coupled to a reference potential node; and a second transistor having a source coupled to the current source path and a drain coupled to the reference potential node.

    COMPACT FREQUENCY-LOCKED LOOP ARCHITECTURE FOR DIGITAL CLOCKING
    5.
    发明公开
    COMPACT FREQUENCY-LOCKED LOOP ARCHITECTURE FOR DIGITAL CLOCKING 审中-公开

    公开(公告)号：US20240297654A1

    公开(公告)日：2024-09-05

    申请号：US18177445

    申请日：2023-03-02

    Applicant: QUALCOMM Incorporated

    Inventor： John ABCARIUS ,  Debesh BHATTA ,  Andrew WEIL ,  Robert Martin ONDRIS ,  Wenjing YIN

    IPC: H03L7/099

    CPC classification number: H03L7/0992

    Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

    QUADRATURE DUTY CYCLE CORRECTION CIRCUIT
    7.
    发明申请
    QUADRATURE DUTY CYCLE CORRECTION CIRCUIT 有权

    公开(公告)号：US20240372535A1

    公开(公告)日：2024-11-07

    申请号：US18312317

    申请日：2023-05-04

    Applicant: QUALCOMM Incorporated

    Inventor： Andrew WEIL ,  Jaswinder SINGH ,  Sameer WADHWA ,  Dongwon SEO

    IPC: H03K3/017 ,  H03K5/156

    Abstract: A duty cycle correction circuit includes four pairs of serially coupled transistors. A first two of the serial pairs of transistors couple between an internal node for complement output clock signal and ground. A second two of the serial pairs of transistors couple between the internal node and a power supply node for a power supply voltage. Each serial pair is controlled by a corresponding pair of quadrature clock signals in which one of the quadrature clock signal is delayed with respect to the other quadrature clock signal be one quarter of a clock period. The first two serial pairs of transistors thus combine to discharge the internal node for one-half clock period whereas the second two serial pairs of transistors combine to charge the internal node for one-half clock period so that the complement output clock signal has a 50% duty cycle.

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