公开(公告)号：US20220416804A1

公开(公告)日：2022-12-29

申请号：US17359918

申请日：2021-06-28

Applicant: QUALCOMM Incorporated

Inventor： Shahin MEHDIZAD TALEIE ,  Dongwon SEO ,  Ashok SWAMINATHAN ,  Gurkanwal Singh SAHOTA ,  Andrew WEIL ,  Haibo FEI

IPC: H03M1/74 ,  H03M1/50 ,  H03M1/78 ,  H03M1/46

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

公开(公告)号：US20190288722A1

公开(公告)日：2019-09-19

申请号：US15962865

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti ASURI ,  Krishnaswamy THIAGARAJAN ,  Ashok SWAMINATHAN ,  Shahin MEHDIZAD TALEIE ,  Yen-Wei CHANG ,  Vinod PANIKKATH ,  Sameer Vasantlal VORA ,  Ayush MITTAL ,  Tonmoy BISWAS ,  Sy-Chyuan HWU ,  Zhilong TANG ,  Ibrahim CHAMAS ,  Ping Wing LAI ,  Behnam SEDIGHI ,  Dongwon SEO ,  Nitz SAPUTRA

IPC: H04B1/04 ,  H04B1/00 ,  H04L27/20

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

公开(公告)号：US20150341025A1

公开(公告)日：2015-11-26

申请号：US14487654

申请日：2014-09-16

Applicant: QUALCOMM Incorporated

Inventor： Derui KONG ,  Sang Min LEE ,  Michael Joseph McGOWAN ,  Dongwon SEO

IPC: H03K17/16

CPC classification number: H03K17/16 ,  H03F1/14 ,  H03F3/45188

Abstract: A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.

Abstract translation: 提供了一种方法和装置。 该装置可以是用于调整电路的净电容的电容元件。 该装置可以被配置为耦合到该电路。 该装置可以被配置为调整电路的净电容以去耦合电路的共模和差分环路带宽调整。 电容元件可以包括配置为耦合到电路的差分节点的一对交叉耦合电容器，以及耦合到相应电容器的一对负增益缓冲器。

公开(公告)号：US20240421828A1

公开(公告)日：2024-12-19

申请号：US18335663

申请日：2023-06-15

Applicant: QUALCOMM Incorporated

Inventor： Haibo FEI ,  Xiahan ZHOU ,  Dongwon SEO ,  Parisa MAHMOUDIDARYAN

IPC: H03M1/78 ,  H03M1/10

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

公开(公告)号：US20240204795A1

公开(公告)日：2024-06-20

申请号：US18068941

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Ashok SWAMINATHAN ,  Nitz SAPUTRA ,  Negar RASHIDI ,  Shahin MEHDIZAD TALEIE ,  Chinmaya MISHRA ,  Dongwon SEO ,  Jong Hyeon PARK ,  Sang-June PARK

IPC: H03M1/66 ,  H03M1/82

CPC classification number: H03M1/665 ,  H03M1/82

Abstract: Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and/or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

公开(公告)号：US20230097708A1

公开(公告)日：2023-03-30

申请号：US17448461

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Parisa MAHMOUDIDARYAN ,  Nitz SAPUTRA ,  Dongwon SEO ,  Shahin MEHDIZAD TALEIE

IPC: H03M1/06

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

公开(公告)号：US20240372535A1

公开(公告)日：2024-11-07

申请号：US18312317

申请日：2023-05-04

Applicant: QUALCOMM Incorporated

Inventor： Andrew WEIL ,  Jaswinder SINGH ,  Sameer WADHWA ,  Dongwon SEO

IPC: H03K3/017 ,  H03K5/156

Abstract: A duty cycle correction circuit includes four pairs of serially coupled transistors. A first two of the serial pairs of transistors couple between an internal node for complement output clock signal and ground. A second two of the serial pairs of transistors couple between the internal node and a power supply node for a power supply voltage. Each serial pair is controlled by a corresponding pair of quadrature clock signals in which one of the quadrature clock signal is delayed with respect to the other quadrature clock signal be one quarter of a clock period. The first two serial pairs of transistors thus combine to discharge the internal node for one-half clock period whereas the second two serial pairs of transistors combine to charge the internal node for one-half clock period so that the complement output clock signal has a 50% duty cycle.

公开(公告)号：US20190383924A1

公开(公告)日：2019-12-19

申请号：US16012193

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Shahin MEHDIZAD TALEIE ,  Chen JIANG ,  Dongwon SEO ,  Udara FERNANDO ,  Shrenik PATEL ,  Roberto RIMINI ,  Anant GUPTA

IPC: G01S13/34 ,  G01S13/02 ,  H04L27/36 ,  H04L27/38 ,  H04B1/40 ,  H03M1/66

Abstract: Certain aspects of the present disclosure generally relate to a programmable multi-mode digital-to-analog converter (DAC) for generating a frequency-modulated signal. For example, certain aspects provide a circuit for sweeping a frequency of an output signal. The circuit generally includes a DAC having an input coupled to an input path of the circuit and an output coupled to an output path of the circuit, a first mixer selectively incorporated in the input path coupled to the input of the DAC, and a second mixer selectively incorporated in the output path coupled to the output of the DAC.

公开(公告)号：US20250062754A1

公开(公告)日：2025-02-20

申请号：US18449552

申请日：2023-08-14

Applicant: QUALCOMM Incorporated

Inventor： Shahin MEHDIZAD TALEIE ,  Dongwon SEO ,  Bhushan Shanti ASURI ,  Ibrahim Ramez CHAMAS ,  Huan WANG ,  Zhiheng WANG ,  Reza RODD

IPC: H03K5/01 ,  H03K19/20

Abstract: Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.

公开(公告)号：US20210391871A1

公开(公告)日：2021-12-16

申请号：US17337619

申请日：2021-06-03

Applicant: QUALCOMM Incorporated

Inventor： Xilin LIU ,  Nitz SAPUTRA ,  Behnam SEDIGHI ,  Ashok SWAMINATHAN ,  Dongwon SEO

IPC: H03M1/74 ,  G05F3/26 ,  H04B1/04

Abstract: Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.