公开(公告)号：US20180175034A1

公开(公告)日：2018-06-21

申请号：US15387501

申请日：2016-12-21

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Jean RICHAUD

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0694 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42392

Abstract: An integrated circuit device may include a p-type metal oxide semiconductor (PMOS) transistor supported by a backside of an isolation layer. The integrated circuit device may also include an n-type metal oxide semiconductor (NMOS) transistor supported by a front-side of the isolation layer, opposite the backside. The integrated circuit device may further include a shared contact extending through the isolation layer and electrically coupling a first terminal of the PMOS transistor to the first terminal of the NMOS transistor.

公开(公告)号：US20210257488A1

公开(公告)日：2021-08-19

申请号：US16792384

申请日：2020-02-17

Applicant: QUALCOMM Incorporated

Inventor： Jean RICHAUD ,  George Pete IMTHURN

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66

Abstract: Certain aspects of the present disclosure generally relate to electrically erasable programmable read-only memory (EEPROM) device comprising at least one EEPROM cell structure. The EEPROM device generally includes a first active region, a second active region, a channel region disposed between the first active region and the second active region, a floating gate structure disposed above the channel region and separated from the channel region by a first dielectric layer, a control gate structure disposed above the floating gate structure and separated from the floating gate structure by a second dielectric layer, and a bottom gate structure disposed below the channel region.