公开(公告)号：US20220109441A1

公开(公告)日：2022-04-07

申请号：US17061314

申请日：2020-10-01

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Ravi Pramod Kumar VEDULA ,  Sivakumar KUMARASAMY

IPC: H03K17/687 ,  H01L27/06 ,  H01L21/8234

Abstract: A radio frequency integrated circuit (RFIC) is described. The RFIC includes a field effect transistor (FET). The FET has a ferroelectric gate stack having a source region, a drain region, a body region, and a gate. The RFIC also includes a first resistor coupled between a first bias supply and the body region. The RFIC further includes a second resistor coupled between the gate and a second bias supply.

公开(公告)号：US20210351811A1

公开(公告)日：2021-11-11

申请号：US17150610

申请日：2021-01-15

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  George Pete IMTHURN ,  Anton ARRIAGADA ,  Sinan GOKTEPELI

IPC: H04B1/44 ,  H03K17/687

Abstract: A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

公开(公告)号：US20190131454A1

公开(公告)日：2019-05-02

申请号：US15800916

申请日：2017-11-01

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238

Abstract: A semiconductor device includes a porous silicon layer on a silicon substrate. A strain inducing intermediate layer (SIIL) is on the porous silicon layer. A silicon layer is on the SIIL. Lattice constant of the silicon layer is different from lattice constant of the SIIL. Thus, the silicon layer is strained. By employing different strain inducing materials in the SIIL, the silicon layer can be used to form different complementary metal oxide semiconductor (CMOS) transistors with improved characteristics.

公开(公告)号：US20190109232A1

公开(公告)日：2019-04-11

申请号：US16152105

申请日：2018-10-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Sivakumar KUMARASAMY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/40

Abstract: An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.

公开(公告)号：US20180061760A1

公开(公告)日：2018-03-01

申请号：US15245087

申请日：2016-08-23

Applicant: QUALCOMM Incorporated

Inventor： Perry Wyan LOU ,  Sinan GOKTEPELI

IPC: H01L23/528 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/768 ,  H01L23/66

CPC classification number: H01L23/5283 ,  H01L21/76889 ,  H01L21/76892 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/66 ,  H01L29/456 ,  H01L2224/11

Abstract: An integrated circuit device may include a front-side contact coupled to a front-side metallization. The integrated circuit device may further include a backside contact coupled to a backside metallization. The front-side contact may be directly coupled to the backside contact.

公开(公告)号：US20170373445A1

公开(公告)日：2017-12-28

申请号：US15669096

申请日：2017-08-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI

IPC: H01R13/6599 ,  H01L29/40 ,  H01R13/6581 ,  H01L27/32

CPC classification number: H01L23/5225 ,  H01L23/481 ,  H01L23/66 ,  H01L27/3272 ,  H01L29/4175 ,  H01L31/02164 ,  H01L2223/6677 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2924/1421

Abstract: An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include backside metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the backside metallization. The integrated RF circuit structure may further include front-side metallization coupled to the backside metallization with a via. The front-side metallization is arranged distal from the backside metallization. The front-side metallization, the via, and the backside metallization may at least partially enclose the active device.

公开(公告)号：US20200373315A1

公开(公告)日：2020-11-26

申请号：US16419606

申请日：2019-05-22

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  George Pete IMTHURN ,  Sinan GOKTEPELI ,  Sivakumar KUMARASAMY

IPC: H01L27/11521 ,  H01L29/788 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L29/66

Abstract: Certain aspects of the present disclosure are generally directed to non-volatile memory (NVM) and techniques for operating and fabricating NVM. Certain aspects provide a memory cell for implementing NVM. The memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between and having a different doping type than the first and third semiconductor regions. The memory cell also includes a fourth semiconductor region disposed adjacent to and having the same doping type as the third semiconductor region, a first front gate region disposed adjacent to the second semiconductor region, and a first floating front gate region disposed adjacent to the third semiconductor region. In certain aspects, the memory cell includes a back gate region, wherein the second semiconductor region is between the first front gate region and at least a portion of the back gate region.

公开(公告)号：US20200091294A1

公开(公告)日：2020-03-19

申请号：US16690454

申请日：2019-11-21

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Yun Han CHU ,  Qingqing LIANG

IPC: H01L29/10 ,  H01L29/45 ,  H01L27/12 ,  H01L21/84 ,  H01L21/74 ,  H01L21/285

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

公开(公告)号：US20200013884A1

公开(公告)日：2020-01-09

申请号：US16027002

申请日：2018-07-03

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Plamen Vassilev KOLEV ,  Peter Graeme CLARKE

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/02

Abstract: A Bipolar Junction Transistor (BJT) comprises an emitter, a collector, and a base between the emitter and the collector. The BJT also comprises an emitter contact on a first side of the BJT, a base contact on the first side of the BJT, and a collector contact on a second side of the BJT. The BJT further comprises a Deep Trench Isolation (DTI) region extending from the first side of the BJT to the second side of the BJT.

公开(公告)号：US20190393340A1

公开(公告)日：2019-12-26

申请号：US16156729

申请日：2018-10-10

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Ravi Pramod Kumar VEDULA ,  Sivakumar KUMARASAMY ,  George Pete IMTHURN ,  Sinan GOKTEPELI

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L21/28

Abstract: An integrated circuit is described. The integrated circuit includes a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET is on a first surface of an insulator layer of the integrated circuit. The MOSFET including a source region, a drain region, and a front gate. The MOSFET also includes an extended drain region between the drain region and a well proximate the front gate. The integrated circuit also includes back gates on a second surface opposite the first surface of the insulator layer. The back gates are overlapped by the extended drain region.