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公开(公告)号：US20230092394A1
公开(公告)日：2023-03-23
申请号：US17478694
申请日：2021-09-17
Applicant: QUALCOMM Incorporated
Inventor： Ashokanand NEELAMBARAN , Piyush GUPTA , Kalyan Kumar BHIRAVABHATLA , Tao WANG , Andrew Evan GRUBER
IPC: G06T1/20 , G06T11/40 , G06T3/40 , A63F13/525
Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of primitives associated with one or more frames in a scene, a portion of the scene being associated with an upscaled sample space and/or a downscaled sample space. The apparatus may also perform a binning pass for the plurality of primitives, the binning pass being associated with an unscaled sample space, where the binning pass sorts each of the primitives into one or more bins associated with each of the one or more frames. Further, the apparatus may perform one of one or more rendering passes for each of the one or more bins. The apparatus may also rasterize each of the plurality of primitives based on at least one of the upscaled sample space or the downscaled sample space.
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公开(公告)号：US20230017522A1
公开(公告)日：2023-01-19
申请号：US17373704
申请日：2021-07-12
Applicant: QUALCOMM Incorporated
Inventor： Sreyas KURUMANGHAT , Kalyan Kumar BHIRAVABHATLA , Andrew Evan GRUBER , Tao WANG , Baoguang YANG , Pavan Kumar AKKARAJU
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a portion of a GPU to include at least one depth processing block, the at least one depth processing block being associated with at least one depth buffer. The apparatus may also identify one or more depth passes of each of a plurality of graphics workloads, the plurality of graphics workloads being associated with a plurality of frames. Further, the apparatus may process each of the one or more depth passes in the portion of the GPU including the at least one depth processing block, each of the one or more depth passes being processed by the at least one depth processing block, the one or more depth passes being associated with the at least one depth buffer.
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3.发明申请公开(公告)号：US20220261958A1
公开(公告)日：2022-08-18
申请号：US17177684
申请日：2021-02-17
Applicant: QUALCOMM Incorporated
Inventor： Pavan Kumar AKKARAJU , Shwetank SINGH , Siva Rama Krishna Reddy BOGI REDDY , Kalyan Kumar BHIRAVABHATLA
Abstract: The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes rendering, by a graphics processing unit (GPU), a first image using a subset of data in a frame buffer corresponding to a first frame, the first image being rendered at a first resolution, the first image comprising a plurality of color component values; generating, using a neural network, a second image corresponding to a higher resolution version of the first image, the second image having a second resolution higher than the first resolution, wherein the neural network uses as input the first image and one or more non-color information corresponding to the first frame and computed by the GPU; and outputting the second image for display.
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公开(公告)号：US20210287427A1
公开(公告)日：2021-09-16
申请号：US16816150
申请日：2020-03-11
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan GRUBER , Krishnaiah GUMMIDIPUDI , Pavan Kumar AKKARAJU , Kalyan Kumar BHIRAVABHATLA , Ankit Kumar SINGH , Sharad RAJ
Abstract: The present disclosure relates to methods and apparatus for graphics processing. The present disclosure can calculate a center-edge distance of a first pixel, the center-edge distance of the first pixel equal to a distance from a first pixel center to one or more edges of a first primitive. Additionally, the present disclosure can store the center-edge distance of the first pixel when the first primitive is visible in a scene. The present disclosure can also determine an amount of overlap between the first pixel and the first primitive. Further, the present disclosure can blend a color of the first pixel with a color of a second pixel based on at least one of the center-edge distance of the first pixel or the amount of overlap between the first pixel and the first primitive.
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公开(公告)号：US20240370967A1
公开(公告)日：2024-11-07
申请号：US18777430
申请日：2024-07-18
Applicant: QUALCOMM Incorporated
Inventor： Kalyan Kumar BHIRAVABHATLA , Andrew Evan GRUBER , Rahul Sunil KUKREJA , Vishwanath Shashikant NIKAM , Tao WANG , Jian LIANG
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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Patent Agency Ranking
公开(公告)号：US20240104684A1
公开(公告)日：2024-03-28
申请号：US17935031
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Kalyan Kumar BHIRAVABHATLA , Andrew Evan GRUBER , Rahul Sunil KUKREJA , Vishwanath Shashikant NIKAM , Tao WANG , Jian LIANG
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US20220327654A1
公开(公告)日：2022-10-13
申请号：US17229697
申请日：2021-04-13
Applicant: QUALCOMM Incorporated
Inventor： Vishwanath Shashikant NIKAM , Kalyan Kumar BHIRAVABHATLA , Suvam CHATTERJEE , Siva Satyanarayana KOLA , Abhishek LAL , Andrew Evan GRUBER
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.
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公开(公告)号：US20210209827A1
公开(公告)日：2021-07-08
申请号：US16733919
申请日：2020-01-03
Applicant: QUALCOMM Incorporated
IPC: G06T15/00
Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine at least some shading data for each of a plurality of patches. Further, aspects of the present disclosure can store the at least some shading data for each of the plurality of patches in a GMEM. Additionally, aspects of the present disclosure can communicate the at least some shading data for each of the plurality of patches. In some aspects, the present disclosure can configure the GMEM for storing the at least some shading data for each of a plurality of patches. Aspects of the present disclosure can also calculate when the GMEM has stored a maximum amount of shading data. Moreover, aspects of the present disclosure can divide each of the plurality of patches into one or more sub-patches when the GMEM has stored the maximum amount of shading data.
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公开(公告)号：US20250131638A1
公开(公告)日：2025-04-24
申请号：US18492719
申请日：2023-10-23
Applicant: QUALCOMM Incorporated
Inventor： Syamantak MITRA , Anamitra MANI , Geetika MALHOTRA , Kalyan Kumar BHIRAVABHATLA , Alexei Vladimirovich BOURD
Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may perform a ray traversal process for a second frame in a set of frames starting at a first node in a plurality of nodes, where a ray in the ray traversal process previously intersected a first primitive in a first frame, where the first primitive corresponds to a first node ID. The apparatus may also detect whether the ray intersects the first primitive in the second frame. Further, the apparatus may store the first node ID for the first node based on the ray intersecting the first primitive in the second frame, or re-perform the ray traversal process for the second frame starting at a root node in the plurality of nodes based on the ray not intersecting the first primitive in the second frame.
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10.发明公开公开(公告)号：US20240104683A1
公开(公告)日：2024-03-28
申请号：US17934978
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Vishwanath Shashikant NIKAM , Kalyan Kumar BHIRAVABHATLA , Jian LIANG , Zhenbiao MA , Siva Satyanarayana KOLA , Suvam CHATTERJEE
Abstract: The present disclosure relates to methods and apparatus for sharing GPU hardware to generate bin visibility information concurrently for graphics processing. The apparatus can cause a processor to: store, in a GMEM, first data associated with a first graphics processing pass for a first frame of graphics data and second data associated with a second graphics processing pass for a second frame of graphics data. The apparatus can also cause a geometry processor to perform the first graphics processing pass using the first data and a second processor to concurrently perform the second graphics processing pass using the second data such that the first graphics processing pass and the second graphics processing path share the geometry processor. In some aspects, the apparatus can switch the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass at a primitive batch boundary.
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