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公开(公告)号：US20240104684A1
公开(公告)日：2024-03-28
申请号：US17935031
申请日：2022-09-23
发明人： Kalyan Kumar BHIRAVABHATLA , Andrew Evan GRUBER , Rahul Sunil KUKREJA , Vishwanath Shashikant NIKAM , Tao WANG , Jian LIANG
摘要： This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US20230394738A1
公开(公告)日：2023-12-07
申请号：US18035507
申请日：2020-11-09
发明人： Yibin ZHANG , Zilin YING , Yun DU , Heng QI , Jiexia YU , Yang YU , Andrew Evan GRUBER , Jian LIANG , Tao WANG , Alexei Vladimirovich BOURD , Gang ZHONG , Minjie HUANG
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.
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公开(公告)号：US20200020067A1
公开(公告)日：2020-01-16
申请号：US16035372
申请日：2018-07-13
发明人： Jian LIANG , Tao WANG , Chun YU , Andrew Evan GRUBER , Donghyun KIM , Nigel POOLE , Tzun-Wei LEE , Shambhoo KHANDELWAL
摘要： A method, an apparatus, and a computer-readable medium may be configured to perform a binning pass for a first frame. The apparatus may be configured to perform a rendering pass for the first frame in parallel with the binning pass. The apparatus may be configured to enhance efficiency in performing a binning pass and a rendering pass for tile-based rendering, such that the binning pass and rendering pass are performed concurrently. The apparatus may be configured to perform the binning pass using a first hardware pipeline, and may be configured to perform the rendering pass using a second hardware pipeline.
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公开(公告)号：US20240311207A1
公开(公告)日：2024-09-19
申请号：US18184381
申请日：2023-03-15
发明人： Jian LIANG , Hu YI , Tao WANG , Fei XU , Ruobai FENG
CPC分类号： G06F9/5077 , G06F9/5038 , G06F9/5083 , G06F9/544
摘要： Aspects of the disclosure are directed to coordination. In accordance with one aspect, an apparatus including a plurality of slices, wherein each slice of the plurality of slices is configured for distributed information processing; and a plurality of dedicated databuses, wherein each slice of the plurality of slices is coupled to one of the plurality of dedicated databuses and each slice of the plurality of slices is configured for local coordination for the distributed information processing.
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5.发明公开公开(公告)号：US20240104683A1
公开(公告)日：2024-03-28
申请号：US17934978
申请日：2022-09-23
发明人： Vishwanath Shashikant NIKAM , Kalyan Kumar BHIRAVABHATLA , Jian LIANG , Zhenbiao MA , Siva Satyanarayana KOLA , Suvam CHATTERJEE
摘要： The present disclosure relates to methods and apparatus for sharing GPU hardware to generate bin visibility information concurrently for graphics processing. The apparatus can cause a processor to: store, in a GMEM, first data associated with a first graphics processing pass for a first frame of graphics data and second data associated with a second graphics processing pass for a second frame of graphics data. The apparatus can also cause a geometry processor to perform the first graphics processing pass using the first data and a second processor to concurrently perform the second graphics processing pass using the second data such that the first graphics processing pass and the second graphics processing path share the geometry processor. In some aspects, the apparatus can switch the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass at a primitive batch boundary.
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公开(公告)号：US20240078737A1
公开(公告)日：2024-03-07
申请号：US18320792
申请日：2023-05-19
发明人： Jian LIANG , Andrew Evan GRUBER , Tao WANG , Xuefeng TANG , Vishwanath Shashikant NIKAM , Nigel POOLE , Kalyan Kumar BHIRAVABHATLA , Fei XU , Zilin YING
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.
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公开(公告)号：US20200279347A1
公开(公告)日：2020-09-03
申请号：US16290761
申请日：2019-03-01
发明人： Nigel POOLE , Xuefeng TANG , Jian LIANG
摘要： The present disclosure relates to methods and apparatus of operation of a processing unit. The apparatus can update a first context register of one or more context registers based on a first programming state. In some aspects, the one or more context registers can be associated with at least one processing unit cluster in a graphics processing pipeline of the processing unit. The apparatus can execute a first draw call function corresponding to the first programming state. The apparatus can determine whether at least one additional first draw call function corresponds to the first programming state. In some aspects, the at least one additional first draw call function can follow the first draw call function in the graphics processing pipeline. Also, the apparatus can execute the at least one additional first draw call function when the at least one additional first draw call function corresponds to the first programming state.
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公开(公告)号：US20240265486A1
公开(公告)日：2024-08-08
申请号：US18163845
申请日：2023-02-02
发明人： Tao WANG , Ashokanand NEELAMBARAN , Jian LIANG , Xiayang ZHAO , Lingjun CHEN
摘要： This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for backface culling for guard band clipping primitives. A graphics processor may identify at least one backface primitive in a set of primitives that extends beyond at least one guard band, where the at least one backface primitive is identified based on a set of fixed point coordinates. The graphics processor may cull the at least one backface primitive. The graphics processor may transmit an indication of the culled at least one backface primitive.
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