公开(公告)号：US20230396253A1

公开(公告)日：2023-12-07

申请号：US17805014

申请日：2022-06-01

Applicant: QUALCOMM Incorporated

Inventor： Kevin BOWLES ,  Chirag MAHESHWARI ,  Divya GANGADHARAN ,  Venkat NARAYANAN ,  Masoud ZAMANI

IPC: H03K19/17736 ,  H03K19/003 ,  H03K19/20

CPC classification number: H03K19/1774 ,  H03K19/17744 ,  H03K19/00323 ,  H03K19/20

Abstract: In certain aspects, an apparatus includes a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus also includes a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further includes a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.

公开(公告)号：US20210409025A1

公开(公告)日：2021-12-30

申请号：US17468945

申请日：2021-09-08

Applicant: QUALCOMM Incorporated

Inventor： Kevin BOWLES ,  Vijay Kiran KALYANAM ,  Sindhuja SUNDARARAJAN

IPC: H03K21/02 ,  H03K23/40 ,  H04B1/40

Abstract: A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.