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公开(公告)号：US20210409025A1
公开(公告)日：2021-12-30
申请号：US17468945
申请日：2021-09-08
Applicant: QUALCOMM Incorporated
Inventor： Kevin BOWLES , Vijay Kiran KALYANAM , Sindhuja SUNDARARAJAN
Abstract: A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.
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公开(公告)号：US20200081479A1
公开(公告)日：2020-03-12
申请号：US16563563
申请日：2019-09-06
Applicant: QUALCOMM Incorporated
Inventor： Vijay Kiran KALYANAM , Eric Wayne MAHURIN
Abstract: A clock gating system (CGS) includes a digital power estimator configured to generate indications of a predicted energy consumption per cycle of a clock signal and a maximum energy consumption per cycle of the clock signal. The CGS further includes a voltage-clock gate (VCG) circuit coupled to the digital power estimator. The VCG circuit is configured to gate and un-gate the clock signal based on the indications prior to occurrence of a voltage droop event and using hardware voltage model circuitry of the VCG circuit. The VCG circuit is further configured to gate the clock signal based on an undershoot phase associated with the voltage droop event and to un-gate the clock signal based on an overshoot phase associated with the voltage droop event.
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