公开(公告)号：US20170046164A1

公开(公告)日：2017-02-16

申请号：US14865150

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Raghavan MADHAVAN ,  Kiran RAVI SETH ,  Yusuf Cagatay TEKMEN ,  Rodney Wayne SMITH

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3838 ,  G06F9/3842

Abstract: A load instruction, for loading a register among a set of registers, is scheduled. Associated with scheduling the load instruction, a register dependency vector, corresponding to the register, is set to a state identifying the load instruction. A consumer instruction is scheduled, having a set of operand register and a target register, the register being in the set of operand registers. A target register dependency vector, corresponding to the target register is set in the memory. Based at least in part on the register being in the set of operand registers, a value of the target register dependency vector identifies the load instruction. Optionally, upon receiving a cache miss notice associated with the load instruction, the target register dependency vector is retrieved.

Abstract translation: 调度用于在一组寄存器中加载寄存器的加载指令。 与调度加载指令相关联，将与寄存器对应的寄存器依赖向量设置为标识加载指令的状态。 消费者指令被调度，具有一组操作数寄存器和目标寄存器，寄存器位于操作数寄存器组中。 在存储器中设置与目标寄存器对应的目标寄存器依赖向量。 至少部分地基于在操作数寄存器组中的寄存器，目标寄存器依赖性向量的值标识加载指令。 可选地，在接收到与加载指令相关联的高速缓存未命中通知时，检索目标寄存器相关性向量。